From patchwork Sat Sep 15 09:25:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 10620907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F026E15A6 for ; Sat, 29 Sep 2018 17:34:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D83F929F18 for ; Sat, 29 Sep 2018 17:34:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CC71529F1C; Sat, 29 Sep 2018 17:34:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=2.0 tests=BAYES_00,DATE_IN_PAST_96_XX, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6C6DB29F18 for ; Sat, 29 Sep 2018 17:34:06 +0000 (UTC) Received: from localhost ([::1]:51735 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J81-0007IT-Nl for patchwork-qemu-devel@patchwork.kernel.org; Sat, 29 Sep 2018 13:34:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6J6j-00062d-1E for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6J6f-0005m9-SM for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:44 -0400 Received: from pio-pvt-msa3.bahnhof.se ([79.136.2.42]:35927) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g6J6f-0005lX-FY for qemu-devel@nongnu.org; Sat, 29 Sep 2018 13:32:41 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa3.bahnhof.se (Postfix) with ESMTP id 0BF503F952; Sat, 29 Sep 2018 19:32:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex): To: ...>, \n \tPhilippe Mathieu-Daud\303\203\302\251 Received: from pio-pvt-msa3.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa3.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cTF4JfJ7TW9f; Sat, 29 Sep 2018 19:32:33 +0200 (CEST) Received: from localhost (h-155-4-135-114.NA.cust.bahnhof.se [155.4.135.114]) (Authenticated sender: mb547485) by pio-pvt-msa3.bahnhof.se (Postfix) with ESMTPA id 7F6333F93B; Sat, 29 Sep 2018 19:32:33 +0200 (CEST) X-Mailbox-Line: From 7c1bbedaf6753f0a3906edf231503726197d2299 Mon Sep 17 00:00:00 2001 Message-Id: <7c1bbedaf6753f0a3906edf231503726197d2299.1538240994.git.noring@nocrew.org> In-Reply-To: References: From: Fredrik Noring Date: Sat, 15 Sep 2018 11:25:37 +0200 To: =?unknown-8bit?q?Aleksandar_Markovic_=3Camarkovic=40wavecomp=2Ecom=3E=2C?= =?unknown-8bit?q?_=22Maciej_W=2E_Rozycki=22_=3Cmacro=40linux-mips=2Eorg=3E?= =?unknown-8bit?q?=2C?= =?unknown-8bit?q?_Philippe_Mathieu-Daud=C3=A9_=3Cf4bug=40amsat=2Eorg=3E?= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 79.136.2.42 Subject: [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?unknown-8bit?q?Peter_Maydell_=3Cpeter=2Emaydell=40linaro=2Eorg=3E=2C_R?= =?unknown-8bit?q?ichard_Henderson_=3Crichard=2Ehenderson=40linaro=2Eorg=3E?= =?unknown-8bit?q?=2C_qemu-devel=40nongnu=2Eorg=2C_J=C3=BCrgen_Urban_=3CJuer?= =?unknown-8bit?q?genUrban=40gmx=2Ede=3E=2C_Petar_Jovanovic_=3Cpjovanovic=40?= =?unknown-8bit?q?wavecomp=2Ecom=3E=2C_Aurelien_Jarno_=3Caurelien=40aurel32?= =?unknown-8bit?q?=2Enet=3E?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The three-operand MULT and MULTU are the only R5900 specific instructions emitted by GCC 7.3. The R5900 also implements the three- operand MADD and MADDU instructions, but they are omitted in QEMU for now since they are absent in programs compiled by current GCC versions. Likewise, the R5900 specific pipeline 1 instruction variants MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are omitted here as well. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index ab16cdb911..7e18ec0d03 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3768,6 +3768,77 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } +/* + * These MULT and MULTU instructions implemented in for example the + * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core + * architectures are special three-operand variants with the syntax + * + * MULT[U] rd, rs, rt + * + * such that + * + * (rd, LO, HI) <- rs * rt + * + * where the low-order 32-bits of the result is placed into both the + * GPR rd and the special register LO. The high-order 32-bits of the + * result is placed into the special register HI. + * + * If the GPR rd is omitted in assembly language, it is taken to be 0, + * which is the zero register that always reads as 0. + */ +static void gen_mul_txxx(DisasContext *ctx, uint32_t opc, + int acc, int rd, int rs, int rt) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_MULT: + { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_muls2_i32(t2, t3, t2, t3); + if (rd) { + tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); + } + tcg_gen_ext_i32_tl(cpu_LO[acc], t2); + tcg_gen_ext_i32_tl(cpu_HI[acc], t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + break; + case OPC_MULTU: + { + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_mulu2_i32(t2, t3, t2, t3); + if (rd) { + tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); + } + tcg_gen_ext_i32_tl(cpu_LO[acc], t2); + tcg_gen_ext_i32_tl(cpu_HI[acc], t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + break; + default: + MIPS_INVAL("mul R5900"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} + static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { @@ -22378,6 +22449,8 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) check_insn(ctx, INSN_VR54XX); op1 = MASK_MUL_VR54XX(ctx->opcode); gen_mul_vr54xx(ctx, op1, rd, rs, rt); + } else if (ctx->insn_flags & INSN_R5900) { + gen_mul_txxx(ctx, op1, 0, rd, rs, rt); } else { gen_muldiv(ctx, op1, rd & 3, rs, rt); }