diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index 2e9656ae1c..53eb9831b2 100644
--- a/hw/display/cg3.c
+++ b/hw/display/cg3.c
@@ -199,65 +199,65 @@ static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
                           unsigned size)
 {
     CG3State *s = opaque;
     uint8_t regval;
     int i;
 
     trace_cg3_write(addr, val, size);
     switch (addr) {
     case CG3_REG_BT458_ADDR:
         s->dac_index = val;
         s->dac_state = 0;
         break;
     case CG3_REG_BT458_COLMAP:
         /* This register can be written to as either a long word or a byte */
         if (size == 1) {
             val <<= 24;
         }
 
         for (i = 0; i < size; i++) {
             regval = val >> 24;
 
             switch (s->dac_state) {
             case 0:
                 s->r[s->dac_index] = regval;
                 s->dac_state++;
                 break;
             case 1:
                 s->g[s->dac_index] = regval;
                 s->dac_state++;
                 break;
             case 2:
                 s->b[s->dac_index] = regval;
                 /* Index autoincrement */
                 s->dac_index = (s->dac_index + 1) & 0xff;
-                /* fall through */
+                fallthrough;
             default:
                 s->dac_state = 0;
                 break;
             }
             val <<= 8;
         }
         s->full_update = 1;
         break;
     case CG3_REG_FBC_CTRL:
         s->regs[0] = val;
         break;
     case CG3_REG_FBC_STATUS:
         if (s->regs[1] & CG3_SR_PENDING_INT) {
             /* clear interrupt */
             s->regs[1] &= ~CG3_SR_PENDING_INT;
             qemu_irq_lower(s->irq);
         }
         break;
     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
         s->regs[addr - 0x10] = val;
         break;
     default:
         qemu_log_mask(LOG_UNIMP,
                   "cg3: Unimplemented register write "
                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
                   addr, size, val);
         break;
     }
 }
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index b80f98b6c4..f1513a084c 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -1319,97 +1319,97 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
 {
     switch (s->vga.sr_index) {
     case 0x00:                  // Standard VGA
     case 0x01:                  // Standard VGA
     case 0x02:                  // Standard VGA
     case 0x03:                  // Standard VGA
     case 0x04:                  // Standard VGA
         s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
         if (s->vga.sr_index == 1)
             s->vga.update_retrace_info(&s->vga);
         break;
     case 0x06:                  // Unlock Cirrus extensions
         val &= 0x17;
         if (val == 0x12) {
             s->vga.sr[s->vga.sr_index] = 0x12;
         } else {
             s->vga.sr[s->vga.sr_index] = 0x0f;
         }
         break;
     case 0x10:
     case 0x30:
     case 0x50:
     case 0x70:                  // Graphics Cursor X
     case 0x90:
     case 0xb0:
     case 0xd0:
     case 0xf0:                  // Graphics Cursor X
         s->vga.sr[0x10] = val;
         s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
         break;
     case 0x11:
     case 0x31:
     case 0x51:
     case 0x71:                  // Graphics Cursor Y
     case 0x91:
     case 0xb1:
     case 0xd1:
     case 0xf1:                  // Graphics Cursor Y
         s->vga.sr[0x11] = val;
         s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
         break;
     case 0x07:                  // Extended Sequencer Mode
         cirrus_update_memory_access(s);
-        /* fall through */
+        fallthrough;
     case 0x08:                  // EEPROM Control
     case 0x09:                  // Scratch Register 0
     case 0x0a:                  // Scratch Register 1
     case 0x0b:                  // VCLK 0
     case 0x0c:                  // VCLK 1
     case 0x0d:                  // VCLK 2
     case 0x0e:                  // VCLK 3
     case 0x0f:                  // DRAM Control
     case 0x13:                  // Graphics Cursor Pattern Address
     case 0x14:                  // Scratch Register 2
     case 0x15:                  // Scratch Register 3
     case 0x16:                  // Performance Tuning Register
     case 0x18:                  // Signature Generator Control
     case 0x19:                  // Signature Generator Result
     case 0x1a:                  // Signature Generator Result
     case 0x1b:                  // VCLK 0 Denominator & Post
     case 0x1c:                  // VCLK 1 Denominator & Post
     case 0x1d:                  // VCLK 2 Denominator & Post
     case 0x1e:                  // VCLK 3 Denominator & Post
     case 0x1f:                  // BIOS Write Enable and MCLK select
         s->vga.sr[s->vga.sr_index] = val;
 #ifdef DEBUG_CIRRUS
         printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
                s->vga.sr_index, val);
 #endif
         break;
     case 0x12:                  // Graphics Cursor Attribute
         s->vga.sr[0x12] = val;
         s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
 #ifdef DEBUG_CIRRUS
         printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
                val, s->vga.force_shadow);
 #endif
         break;
     case 0x17:                  // Configuration Readback and Extended Control
         s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
                                    | (val & 0xc7);
         cirrus_update_memory_access(s);
         break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
                       s->vga.sr_index, val);
         break;
     }
 }
 
 /***************************************
  *
  *  I/O access at 0x3c6
  *
  ***************************************/
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index 1b27b64f6d..e21450d726 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -381,26 +381,26 @@ static void tcx_reset(DeviceState *d)
 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
                               unsigned size)
 {
     TCXState *s = opaque;
     uint32_t val = 0;
 
     switch (s->dac_state) {
     case 0:
         val = s->r[s->dac_index] << 24;
         s->dac_state++;
         break;
     case 1:
         val = s->g[s->dac_index] << 24;
         s->dac_state++;
         break;
     case 2:
         val = s->b[s->dac_index] << 24;
         s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
-        /* fall through */
+        fallthrough;
     default:
         s->dac_state = 0;
         break;
     }
 
     return val;
 }
@@ -408,43 +408,43 @@ static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
                            unsigned size)
 {
     TCXState *s = opaque;
     unsigned index;
 
     switch (addr) {
     case 0: /* Address */
         s->dac_index = val >> 24;
         s->dac_state = 0;
         break;
     case 4:  /* Pixel colours */
     case 12: /* Overlay (cursor) colours */
         if (addr & 8) {
             index = (s->dac_index & 3) + 256;
         } else {
             index = s->dac_index;
         }
         switch (s->dac_state) {
         case 0:
             s->r[index] = val >> 24;
             update_palette_entries(s, index, index + 1);
             s->dac_state++;
             break;
         case 1:
             s->g[index] = val >> 24;
             update_palette_entries(s, index, index + 1);
             s->dac_state++;
             break;
         case 2:
             s->b[index] = val >> 24;
             update_palette_entries(s, index, index + 1);
             s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */
-            /* fall through */
+            fallthrough;
         default:
             s->dac_state = 0;
             break;
         }
         break;
     default: /* Control registers */
         break;
     }
 }
