From patchwork Tue Jul 18 11:55:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 9848203 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5AC9E60393 for ; Tue, 18 Jul 2017 12:07:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0735B2621B for ; Tue, 18 Jul 2017 12:07:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F07B528567; Tue, 18 Jul 2017 12:07:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7ECF126E76 for ; Tue, 18 Jul 2017 12:07:37 +0000 (UTC) Received: from localhost ([::1]:55910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXRHs-00053S-Ph for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Jul 2017 08:07:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXR7T-0003yq-D4 for qemu-devel@nongnu.org; Tue, 18 Jul 2017 07:56:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXR7R-0005Ln-Fy for qemu-devel@nongnu.org; Tue, 18 Jul 2017 07:56:51 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23298) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXR7R-0005LA-6h for qemu-devel@nongnu.org; Tue, 18 Jul 2017 07:56:49 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id D236960FBDC2E; Tue, 18 Jul 2017 12:56:44 +0100 (IST) Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 18 Jul 2017 12:56:47 +0100 From: James Hogan To: Yongbok Kim Date: Tue, 18 Jul 2017 12:55:59 +0100 Message-ID: <7caba6ac0e2f7dd2183f4febc529ceee55c699be.1500378931.git-series.james.hogan@imgtec.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 14/14] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Signed-off-by: James Hogan Cc: Yongbok Kim Cc: Aurelien Jarno Reviewed-by: Yongbok Kim --- Changes in v2: - New patch. --- target/mips/translate_init.c | 2 ++ 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index 741b39023744..255d25bacd03 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -640,6 +640,7 @@ static const mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x36FBFFFF, + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), @@ -723,6 +724,7 @@ static const mips_def_t mips_defs[] = .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1U << CP0PG_RIE), .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),