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15 Aug 2019 14:36:03 -0700 IronPort-SDR: 4HPxB2ojzz9R0wPEaoxKVEftqx7w39CUOQ78zDob1dWCJzsUuoBXmShxQ5bz1UzqoOP5mHBIQO bTnqN5TSyIVZncSRUZLnQ6TIirNfqOahvqJc0VdtbcHCpaVMe9f9fYR7mjzsZurWmvzp5Yojfg SOoao3SU9zQbydYU7WFxf8dRqeCHb5kMqikPyD96tTfL0v3WbDHDOm8wklccTzGgKRaeFZRlxj TsYBLrHNrjvss5qYFz4cG1LXqaQF8gGOAVBfiUW6dZrW9kQKhcZqa2d7wYouYhKv6sW5Y5VADh oC4= Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip01.wdc.com with ESMTP; 15 Aug 2019 14:38:33 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Thu, 15 Aug 2019 14:35:04 -0700 Message-Id: <7e476df36a8c2ba53162e9a5f62e9fa171da00ad.1565904855.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.144 Subject: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The mip register is an MXLEN-bit long register. Convert it to a target_ulong type instead of uint32_t. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dc9b17678..0a7985c3f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -130,7 +130,7 @@ struct CPURISCVState { * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. * mip is 32-bits to allow atomic_read on 32-bit hosts. */ - uint32_t mip; + target_ulong mip; uint32_t miclaim; target_ulong mie;