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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id v10-20020a5d678a000000b0032d9f32b96csm569185wru.62.2023.10.13.01.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 01:50:24 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , "Michael S. Tsirkin" , Paolo Bonzini , Peter Maydell , "Edgar E. Iglesias" , Alistair Francis , qemu-arm@nongnu.org (open list:ARM cores) Subject: [RFC PATCH v3 59/78] hw/intc: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 11:46:27 +0300 Message-Id: <8886379aabaa8f02fa7b3b4c57828bd0e4795535.1697186560.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/intc/apic.c | 2 +- hw/intc/arm_gicv3_kvm.c | 16 ++++++++-------- hw/intc/armv7m_nvic.c | 12 ++++++------ hw/intc/xilinx_intc.c | 2 +- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index ac3d47d231..30f341c722 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -183,7 +183,7 @@ void apic_deliver_pic_intr(DeviceState *dev, int level) if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) break; apic_reset_bit(s->irr, lvt & 0xff); - /* fall through */ + fallthrough; case APIC_DM_EXTINT: apic_update_irq(s); break; diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 72ad916d3d..782cef3390 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -479,11 +479,11 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); reg64 = c->icc_apr[GICV3_G0][2]; kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); - /* fall through */ + fallthrough; case 6: reg64 = c->icc_apr[GICV3_G0][1]; kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); - /* fall through */ + fallthrough; default: reg64 = c->icc_apr[GICV3_G0][0]; kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); @@ -495,11 +495,11 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); reg64 = c->icc_apr[GICV3_G1NS][2]; kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); - /* fall through */ + fallthrough; case 6: reg64 = c->icc_apr[GICV3_G1NS][1]; kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); - /* fall through */ + fallthrough; default: reg64 = c->icc_apr[GICV3_G1NS][0]; kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); @@ -636,11 +636,11 @@ static void kvm_arm_gicv3_get(GICv3State *s) c->icc_apr[GICV3_G0][3] = reg64; kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); c->icc_apr[GICV3_G0][2] = reg64; - /* fall through */ + fallthrough; case 6: kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); c->icc_apr[GICV3_G0][1] = reg64; - /* fall through */ + fallthrough; default: kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); c->icc_apr[GICV3_G0][0] = reg64; @@ -652,11 +652,11 @@ static void kvm_arm_gicv3_get(GICv3State *s) c->icc_apr[GICV3_G1NS][3] = reg64; kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); c->icc_apr[GICV3_G1NS][2] = reg64; - /* fall through */ + fallthrough; case 6: kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); c->icc_apr[GICV3_G1NS][1] = reg64; - /* fall through */ + fallthrough; default: kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); c->icc_apr[GICV3_G1NS][0] = reg64; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 03b6b8c986..72d3ae985e 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2224,7 +2224,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, /* reads of set and clear both return the status */ case 0x100 ... 0x13f: /* NVIC Set enable */ offset += 0x80; - /* fall through */ + fallthrough; case 0x180 ... 0x1bf: /* NVIC Clear enable */ val = 0; startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ @@ -2238,7 +2238,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, break; case 0x200 ... 0x23f: /* NVIC Set pend */ offset += 0x80; - /* fall through */ + fallthrough; case 0x280 ... 0x2bf: /* NVIC Clear pend */ val = 0; startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ @@ -2280,7 +2280,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, val = 0; break; } - /* fall through */ + fallthrough; case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ val = 0; for (i = 0; i < size; i++) { @@ -2355,7 +2355,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, case 0x100 ... 0x13f: /* NVIC Set enable */ offset += 0x80; setval = 1; - /* fall through */ + fallthrough; case 0x180 ... 0x1bf: /* NVIC Clear enable */ startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; @@ -2373,7 +2373,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, */ offset += 0x80; setval = 1; - /* fall through */ + fallthrough; case 0x280 ... 0x2bf: /* NVIC Clear pend */ startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ @@ -2408,7 +2408,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { goto exit_ok; } - /* fall through */ + fallthrough; case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ for (i = 0; i < size; i++) { unsigned hdlidx = (offset - 0xd14) + i; diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 6e5012e66e..245f452898 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -131,7 +131,7 @@ static void pic_write(void *opaque, hwaddr addr, if ((p->regs[R_MER] & 2)) { break; } - /* fallthrough */ + fallthrough; default: if (addr < ARRAY_SIZE(p->regs)) p->regs[addr] = value;