diff mbox

[5/9] target-mips: Abstract mmu_idx from hflags

Message ID 8ab0a89634e5cde1eaf41ef34e1a575730d30751.1473159543.git-series.james.hogan@imgtec.com (mailing list archive)
State New, archived
Headers show

Commit Message

James Hogan Sept. 6, 2016, 11:03 a.m. UTC
The MIPS mmu_idx is sometimes calculated from hflags without an env
pointer available as cpu_mmu_index() requires.

Create a common hflags_mmu_index() for the purpose of this calculation
which can operate on any hflags, not just with an env pointer, and
update cpu_mmu_index() itself and gen_intermediate_code() to use it.

This will also allow the logic to be more easily updated when a new MMU
mode is added.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/cpu.h       | 8 +++++++-
 target-mips/translate.c | 2 +-
 2 files changed, 8 insertions(+), 2 deletions(-)

Comments

Yongbok Kim Oct. 7, 2016, 4:08 p.m. UTC | #1
On 06/09/2016 12:03, James Hogan wrote:
> The MIPS mmu_idx is sometimes calculated from hflags without an env
> pointer available as cpu_mmu_index() requires.
> 
> Create a common hflags_mmu_index() for the purpose of this calculation
> which can operate on any hflags, not just with an env pointer, and
> update cpu_mmu_index() itself and gen_intermediate_code() to use it.
> 
> This will also allow the logic to be more easily updated when a new MMU
> mode is added.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Leon Alrae <leon.alrae@imgtec.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-mips/cpu.h       | 8 +++++++-
>  target-mips/translate.c | 2 +-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 6ea2bf14c817..8ddc965e4735 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -695,9 +695,15 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
>  #define MMU_MODE1_SUFFIX _super
>  #define MMU_MODE2_SUFFIX _user
>  #define MMU_USER_IDX 2
> +
> +static inline int hflags_mmu_index(uint32_t hflags)
> +{
> +    return hflags & MIPS_HFLAG_KSU;
> +}
> +
>  static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
>  {
> -    return env->hflags & MIPS_HFLAG_KSU;
> +    return hflags_mmu_index(env->hflags);
>  }
>  
>  static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 8506c39a359c..af17fc95eb8f 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -20004,7 +20004,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
>  #ifdef CONFIG_USER_ONLY
>          ctx.mem_idx = MIPS_HFLAG_UM;
>  #else
> -        ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
> +        ctx.mem_idx = hflags_mmu_index(ctx.hflags);
>  #endif
>      ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
>                                   MO_UNALN : MO_ALIGN;
> 

There are two other lines in the op_helper.c.
1466: switch (env->hflags & MIPS_HFLAG_KSU) {
2242: switch (env->hflags & MIPS_HFLAG_KSU) {

Using the function in the cpu.h also can be considered.

Otherwise,
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>

Regards,
Yongbok
James Hogan July 6, 2017, 8:55 p.m. UTC | #2
On Fri, Oct 07, 2016 at 05:08:46PM +0100, Yongbok Kim wrote:
> On 06/09/2016 12:03, James Hogan wrote:
> > The MIPS mmu_idx is sometimes calculated from hflags without an env
> > pointer available as cpu_mmu_index() requires.
> > 
> > Create a common hflags_mmu_index() for the purpose of this calculation
> > which can operate on any hflags, not just with an env pointer, and
> > update cpu_mmu_index() itself and gen_intermediate_code() to use it.
> > 
> > This will also allow the logic to be more easily updated when a new MMU
> > mode is added.
> > 
> > Signed-off-by: James Hogan <james.hogan@imgtec.com>
> > Cc: Leon Alrae <leon.alrae@imgtec.com>
> > Cc: Aurelien Jarno <aurelien@aurel32.net>
> > ---
> >  target-mips/cpu.h       | 8 +++++++-
> >  target-mips/translate.c | 2 +-
> >  2 files changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> > index 6ea2bf14c817..8ddc965e4735 100644
> > --- a/target-mips/cpu.h
> > +++ b/target-mips/cpu.h
> > @@ -695,9 +695,15 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
> >  #define MMU_MODE1_SUFFIX _super
> >  #define MMU_MODE2_SUFFIX _user
> >  #define MMU_USER_IDX 2
> > +
> > +static inline int hflags_mmu_index(uint32_t hflags)
> > +{
> > +    return hflags & MIPS_HFLAG_KSU;
> > +}
> > +
> >  static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
> >  {
> > -    return env->hflags & MIPS_HFLAG_KSU;
> > +    return hflags_mmu_index(env->hflags);
> >  }
> >  
> >  static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
> > diff --git a/target-mips/translate.c b/target-mips/translate.c
> > index 8506c39a359c..af17fc95eb8f 100644
> > --- a/target-mips/translate.c
> > +++ b/target-mips/translate.c
> > @@ -20004,7 +20004,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
> >  #ifdef CONFIG_USER_ONLY
> >          ctx.mem_idx = MIPS_HFLAG_UM;
> >  #else
> > -        ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
> > +        ctx.mem_idx = hflags_mmu_index(ctx.hflags);
> >  #endif
> >      ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
> >                                   MO_UNALN : MO_ALIGN;
> > 
> 
> There are two other lines in the op_helper.c.
> 1466: switch (env->hflags & MIPS_HFLAG_KSU) {
> 2242: switch (env->hflags & MIPS_HFLAG_KSU) {
> 
> Using the function in the cpu.h also can be considered.

Yeh, I avoided changing these as it wasn't clear if they were interested
in just logging the mode from KSU, or specifically the mmu index (i.e.
to answer "what address space am I looking at?"), and it looked more
like the former given the reference to MIPS_HFLAG_{UM,SM,KM}
definitions.

I've now changed them both to effecitvely log the mmu index, changing
the MIPS_HFLAG_{UM,SM,KM} references to literal numbers as used
elsewhere when comparing MMU indicies.

Cheers
James
diff mbox

Patch

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6ea2bf14c817..8ddc965e4735 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -695,9 +695,15 @@  extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 #define MMU_MODE1_SUFFIX _super
 #define MMU_MODE2_SUFFIX _user
 #define MMU_USER_IDX 2
+
+static inline int hflags_mmu_index(uint32_t hflags)
+{
+    return hflags & MIPS_HFLAG_KSU;
+}
+
 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 {
-    return env->hflags & MIPS_HFLAG_KSU;
+    return hflags_mmu_index(env->hflags);
 }
 
 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8506c39a359c..af17fc95eb8f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20004,7 +20004,7 @@  void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
 #ifdef CONFIG_USER_ONLY
         ctx.mem_idx = MIPS_HFLAG_UM;
 #else
-        ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
+        ctx.mem_idx = hflags_mmu_index(ctx.hflags);
 #endif
     ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
                                  MO_UNALN : MO_ALIGN;