From patchwork Tue Sep 6 11:03:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 9316375 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 77E3C60752 for ; Tue, 6 Sep 2016 11:04:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6AFE128C85 for ; Tue, 6 Sep 2016 11:04:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5FBB428C87; Tue, 6 Sep 2016 11:04:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BE71828C85 for ; Tue, 6 Sep 2016 11:04:57 +0000 (UTC) Received: from localhost ([::1]:60667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhEBU-0004VU-Tl for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Sep 2016 07:04:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52980) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhEAs-0004Rk-IQ for qemu-devel@nongnu.org; Tue, 06 Sep 2016 07:04:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhEAm-00022G-EH for qemu-devel@nongnu.org; Tue, 06 Sep 2016 07:04:17 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:41660) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhEAm-000221-8N for qemu-devel@nongnu.org; Tue, 06 Sep 2016 07:04:12 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 245F5F85B88E4; Tue, 6 Sep 2016 12:03:58 +0100 (IST) Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 6 Sep 2016 12:04:00 +0100 From: James Hogan To: Leon Alrae Date: Tue, 6 Sep 2016 12:03:40 +0100 Message-ID: <8ab0a89634e5cde1eaf41ef34e1a575730d30751.1473159543.git-series.james.hogan@imgtec.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 5/9] target-mips: Abstract mmu_idx from hflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The MIPS mmu_idx is sometimes calculated from hflags without an env pointer available as cpu_mmu_index() requires. Create a common hflags_mmu_index() for the purpose of this calculation which can operate on any hflags, not just with an env pointer, and update cpu_mmu_index() itself and gen_intermediate_code() to use it. This will also allow the logic to be more easily updated when a new MMU mode is added. Signed-off-by: James Hogan Cc: Leon Alrae Cc: Aurelien Jarno Reviewed-by: Yongbok Kim --- target-mips/cpu.h | 8 +++++++- target-mips/translate.c | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6ea2bf14c817..8ddc965e4735 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -695,9 +695,15 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user #define MMU_USER_IDX 2 + +static inline int hflags_mmu_index(uint32_t hflags) +{ + return hflags & MIPS_HFLAG_KSU; +} + static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) { - return env->hflags & MIPS_HFLAG_KSU; + return hflags_mmu_index(env->hflags); } static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) diff --git a/target-mips/translate.c b/target-mips/translate.c index 8506c39a359c..af17fc95eb8f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20004,7 +20004,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) #ifdef CONFIG_USER_ONLY ctx.mem_idx = MIPS_HFLAG_UM; #else - ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU; + ctx.mem_idx = hflags_mmu_index(ctx.hflags); #endif ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN;