diff mbox series

[3/7] target/mips: Add MXU instruction S8LDD

Message ID 8c9d8af290bc2086b6d685632bc49806cfd40d0a.1535133089.git.jancraig@amazon.com (mailing list archive)
State New, archived
Headers show
Series Add limited MXU instruction support | expand

Commit Message

Gonglei (Arei)" via Aug. 24, 2018, 7:44 p.m. UTC 
Adds support for emulating the S8LDD MXU instruction.

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
---
 target/mips/translate.c | 82 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 81 insertions(+), 1 deletion(-)

Comments

Richard Henderson Aug. 25, 2018, 5:17 p.m. UTC | #1 
On 08/24/2018 12:44 PM, Craig Janeczek via Qemu-devel wrote:
> +    case OPC_MXU_S8LDD:
> +        gen_load_gpr(t0, opcode->S8LDD.rb);
> +        tcg_gen_movi_tl(t1, opcode->S8LDD.s8);
> +        tcg_gen_ext8s_tl(t1, t1);
> +        tcg_gen_add_tl(t0, t0, t1);

This is

  gen_load_gpr(t0, rb);
  tcg_gen_addi_tl(t0, t0, (int8_t)s8);

> +        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);

You might want MO_UB so that you don't need

  tcg_gen_andi_tl(t1, t1, 0xff)

in several places.

Hmm.  Of course there's the two sign-extend cases that do want this.  So maybe
some more logic above the load is warranted.

> +        switch (opcode->S8LDD.optn3) {
> +        case 0: /*XRa[7:0] = tmp8 */
> +            tcg_gen_andi_tl(t1, t1, 0xFF);
> +            gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
> +            tcg_gen_andi_tl(t0, t0, 0xFFFFFF00);
> +            tcg_gen_or_tl(t0, t0, t1);

  gen_load_mxu_gpr(t0, xra);
  tcg_gen_deposit_tl(t0, t0, t1, 0, 8);

> +            break;
> +        case 1: /* XRa[15:8] = tmp8 */
> +            tcg_gen_andi_tl(t1, t1, 0xFF);
> +            gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
> +            tcg_gen_andi_tl(t0, t0, 0xFFFF00FF);
> +            tcg_gen_shli_tl(t1, t1, 8);
> +            tcg_gen_or_tl(t0, t0, t1);

  tcg_gen_deposit_tl(t0, t0, t1, 8, 8);

> +        case 4: /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
> +            tcg_gen_andi_tl(t1, t1, 0xFF);
> +            tcg_gen_mov_tl(t0, t1);
> +            tcg_gen_shli_tl(t1, t1, 16);
> +            tcg_gen_or_tl(t0, t0, t1);
> +            break;

  tcg_gen_deposit_tl(t0, t1, t1, 16, 16);

> +        case 5: /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
> +            tcg_gen_andi_tl(t1, t1, 0xFF);
> +            tcg_gen_shli_tl(t1, t1, 8);
> +            tcg_gen_mov_tl(t0, t1);
> +            tcg_gen_shli_tl(t1, t1, 16);
> +            tcg_gen_or_tl(t0, t0, t1);

  tcg_gen_shli_tl(t1, t1, 8);
  tcg_gen_deposit_tl(t0, t1, t1, 16, 16);

> +        case 7: /* XRa = {tmp8, tmp8, tmp8, tmp8} */
> +            tcg_gen_andi_tl(t1, t1, 0xFF);
> +            tcg_gen_mov_tl(t0, t1);
> +            tcg_gen_shli_tl(t1, t1, 8);
> +            tcg_gen_or_tl(t0, t0, t1);
> +            tcg_gen_shli_tl(t1, t1, 8);
> +            tcg_gen_or_tl(t0, t0, t1);
> +            tcg_gen_shli_tl(t1, t1, 8);
> +            tcg_gen_or_tl(t0, t0, t1);

  tcg_gen_muli_tl(t0, t1, 0x01010101);


r~
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 381dfad36e..4ccccd5849 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -365,6 +365,7 @@  enum {
     OPC_DCLZ     = 0x24 | OPC_SPECIAL2,
     OPC_DCLO     = 0x25 | OPC_SPECIAL2,
     /* MXU */
+    OPC_MXU_S8LDD  = 0x22 | OPC_SPECIAL2,
     OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2,
     OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2,
     /* Special */
@@ -3784,14 +3785,24 @@  typedef union {
         uint32_t:5;
         uint32_t special2:6;
     } S32M2I;
+
+    struct {
+        uint32_t op:6;
+        uint32_t xra:4;
+        uint32_t s8:8;
+        uint32_t optn3:3;
+        uint32_t rb:5;
+        uint32_t special2:6;
+    } S8LDD;
 } MXU_OPCODE;
 
 /* MXU Instructions */
 static void gen_mxu(DisasContext *ctx, uint32_t opc)
 {
 #ifndef TARGET_MIPS64 /* Only works in 32 bit mode */
-    TCGv t0;
+    TCGv t0, t1;
     t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
     MXU_OPCODE *opcode = (MXU_OPCODE *)&ctx->opcode;
 
     switch (opc) {
@@ -3804,9 +3815,77 @@  static void gen_mxu(DisasContext *ctx, uint32_t opc)
         gen_load_mxu_gpr(t0, opcode->S32M2I.xra);
         gen_store_gpr(t0, opcode->S32M2I.rb);
         break;
+
+    case OPC_MXU_S8LDD:
+        gen_load_gpr(t0, opcode->S8LDD.rb);
+        tcg_gen_movi_tl(t1, opcode->S8LDD.s8);
+        tcg_gen_ext8s_tl(t1, t1);
+        tcg_gen_add_tl(t0, t0, t1);
+        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);
+        switch (opcode->S8LDD.optn3) {
+        case 0: /*XRa[7:0] = tmp8 */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
+            tcg_gen_andi_tl(t0, t0, 0xFFFFFF00);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 1: /* XRa[15:8] = tmp8 */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
+            tcg_gen_andi_tl(t0, t0, 0xFFFF00FF);
+            tcg_gen_shli_tl(t1, t1, 8);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 2: /* XRa[23:16] = tmp8 */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
+            tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);
+            tcg_gen_shli_tl(t1, t1, 16);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 3: /* XRa[31:24] = tmp8 */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
+            tcg_gen_andi_tl(t0, t0, 0x00FFFFFF);
+            tcg_gen_shli_tl(t1, t1, 24);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 4: /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            tcg_gen_mov_tl(t0, t1);
+            tcg_gen_shli_tl(t1, t1, 16);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 5: /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            tcg_gen_shli_tl(t1, t1, 8);
+            tcg_gen_mov_tl(t0, t1);
+            tcg_gen_shli_tl(t1, t1, 16);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 6: /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
+            tcg_gen_mov_tl(t0, t1);
+            tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);
+            tcg_gen_shli_tl(t1, t1, 16);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        case 7: /* XRa = {tmp8, tmp8, tmp8, tmp8} */
+            tcg_gen_andi_tl(t1, t1, 0xFF);
+            tcg_gen_mov_tl(t0, t1);
+            tcg_gen_shli_tl(t1, t1, 8);
+            tcg_gen_or_tl(t0, t0, t1);
+            tcg_gen_shli_tl(t1, t1, 8);
+            tcg_gen_or_tl(t0, t0, t1);
+            tcg_gen_shli_tl(t1, t1, 8);
+            tcg_gen_or_tl(t0, t0, t1);
+            break;
+        }
+        gen_store_mxu_gpr(t0, opcode->S8LDD.xra);
+        break;
     }
 
     tcg_temp_free(t0);
+    tcg_temp_free(t1);
 #else
     generate_exception_end(ctx, EXCP_RI);
 #endif
@@ -17895,6 +17974,7 @@  static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
 
     case OPC_MXU_S32I2M:
     case OPC_MXU_S32M2I:
+    case OPC_MXU_S8LDD:
         gen_mxu(ctx, op1);
         break;