[v3,2/8] target/riscv: Define ePMP mseccfg

Commit Message

Alistair Francis April 13, 2021, 2:41 a.m. UTC

From: Hou Weiying <[e-mail]>

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <[e-mail]>
Signed-off-by: Hou Weiying <[e-mail]>
Signed-off-by: Myriad-Dreamin <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Message-Id: <[e-mail]>
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <[e-mail]>
Reviewed-by: Bin Meng <[e-mail]>
---
 target/riscv/cpu_bits.h | 3 +++
 1 file changed, 3 insertions(+)

Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8549d77b4f..24d89939a0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -220,6 +220,9 @@ 
 #define CSR_MTINST          0x34a
 #define CSR_MTVAL2          0x34b
 
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG         0x390
+#define CSR_MSECCFGH        0x391
 /* Physical Memory Protection */
 #define CSR_PMPCFG0         0x3a0
 #define CSR_PMPCFG1         0x3a1