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[37.6.0.26]) by smtp.gmail.com with ESMTPSA id a10-20020a05600c224a00b003fe23b10fdfsm1798183wmm.36.2023.10.13.01.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 01:00:10 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , Jonathan Cameron , Fan Ni Subject: [RFC PATCH v2 74/78] hw/cxl/cxl-device-utils.c: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:57:41 +0300 Message-Id: <93054ef7101216c752d26bbd4011e612ff67010d.1697183699.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/cxl/cxl-device-utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c index bd68328032..63f009847e 100644 --- a/hw/cxl/cxl-device-utils.c +++ b/hw/cxl/cxl-device-utils.c @@ -78,18 +78,18 @@ static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size) static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset, uint64_t value) { switch (offset) { case A_CXL_DEV_MAILBOX_CTRL: - /* fallthrough */ + fallthrough; case A_CXL_DEV_MAILBOX_CAP: /* RO register */ break; default: qemu_log_mask(LOG_UNIMP, "%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n", __func__, offset); return; } reg_state[offset / sizeof(*reg_state)] = value; } @@ -97,22 +97,22 @@ static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset, static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset, uint64_t value) { switch (offset) { case A_CXL_DEV_MAILBOX_CMD: break; case A_CXL_DEV_BG_CMD_STS: /* BG not supported */ - /* fallthrough */ + fallthrough; case A_CXL_DEV_MAILBOX_STS: /* Read only register, will get updated by the state machine */ return; default: qemu_log_mask(LOG_UNIMP, "%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n", __func__, offset); return; } reg_state[offset / sizeof(*reg_state)] = value; }