| Message ID | 942cea1d0a0ec0ba2ba54df4c04693dfac75c331.1654256190.git.research_trasio@irq.a4lg.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Make CPU property names lowercase (w/ capitalized aliases) | expand |
On Fri, Jun 3, 2022 at 9:36 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Because many developers introduced new properties in various ways, the > entire riscv_cpu_properties block is getting too complex. > > This commit reorganizes riscv_cpu_properties for clarity on future. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 64 +++++++++++++++++++++++++++------------------- > 1 file changed, 37 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a91253d4bd..3f21563f2d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -840,7 +840,7 @@ static void riscv_cpu_init(Object *obj) > } > > static Property riscv_cpu_properties[] = { > - /* Defaults for standard extensions */ > + /* Base ISA and single-letter standard extensions */ > DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), > DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), > DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), > @@ -853,29 +853,17 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), > - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > + > + /* Standard unprivileged extensions */ > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > + > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > - > - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > - > - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), > - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), > - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), > - > - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > - DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > - DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), > + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), > + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), > + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), > > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > @@ -884,6 +872,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), > DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > + > DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), > DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), > DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), > @@ -895,10 +884,31 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), > DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), > > - DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), > - DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), > - DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), > - DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), > + DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > + DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > + > + /* Standard supervisor-level extensions */ > + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > + > + /* Base features */ > + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > + > + /* ISA specification / extension versions */ > + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > + > + /* CPU parameters */ > + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), > + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), > + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), > + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), > @@ -909,9 +919,9 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), > > - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > - > + /* Other options */ > DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), > + > DEFINE_PROP_END_OF_LIST(), > }; > > -- > 2.34.1 >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a91253d4bd..3f21563f2d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -840,7 +840,7 @@ static void riscv_cpu_init(Object *obj) } static Property riscv_cpu_properties[] = { - /* Defaults for standard extensions */ + /* Base ISA and single-letter standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), @@ -853,29 +853,17 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + + /* Standard unprivileged extensions */ DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), - - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), - - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), - DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), - DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), @@ -884,6 +872,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), @@ -895,10 +884,31 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), - DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), - DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), - DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), - DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), + DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), + DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), + + /* Standard supervisor-level extensions */ + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), + + /* Base features */ + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + + /* ISA specification / extension versions */ + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + + /* CPU parameters */ + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), @@ -909,9 +919,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), - + /* Other options */ DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), + DEFINE_PROP_END_OF_LIST(), };
Because many developers introduced new properties in various ways, the entire riscv_cpu_properties block is getting too complex. This commit reorganizes riscv_cpu_properties for clarity on future. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> --- target/riscv/cpu.c | 64 +++++++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 27 deletions(-)