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PCL:0; RULEID:(601004)(2401047)(13023025)(13017025)(13015025)(13018025)(13024025)(520078)(5005006)(8121501046)(3002001)(10201501046); SRVR:CY1NAM02HT134; BCL:0; PCL:0; RULEID:; SRVR:CY1NAM02HT134; X-Forefront-PRVS: 0826B2F01B X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2016 22:37:36.7580 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT134 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.80 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH v2 06/16] register: QOMify X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peter Crosthwaite QOMify registers as a child of TYPE_DEVICE. This allows registers to define GPIOs. Define an init helper that will do QOM initialisation as well as setup the r/w fast paths. Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis Reviewed-by: KONRAD Frederic --- hw/core/register.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/register.h | 17 +++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/hw/core/register.c b/hw/core/register.c index ca10cff..000b87f 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -185,6 +185,28 @@ void register_reset(RegisterInfo *reg) register_write_val(reg, reg->access->reset); } +void register_init(RegisterInfo *reg) +{ + assert(reg); + const RegisterAccessInfo *ac; + + if (!reg->data || !reg->access) { + return; + } + + object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER); + + ac = reg->access; + + /* if there are no debug msgs and no RMW requirement, mark for fast write */ + reg->write_lite = reg->debug || ac->ro || ac->w1c || ac->pre_write || + ((ac->ge0 || ac->ge1) && qemu_loglevel_mask(LOG_GUEST_ERROR)) || + ((ac->ui0 || ac->ui1) && qemu_loglevel_mask(LOG_UNIMP)) + ? false : true; + /* no debug and no clear-on-read is a fast read */ + reg->read_lite = reg->debug || ac->cor ? false : true; +} + static inline void register_write_memory(void *opaque, hwaddr addr, uint64_t value, unsigned size, bool be) { @@ -232,3 +254,15 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size) { return register_read_memory(opaque, addr, size, false); } + +static const TypeInfo register_info = { + .name = TYPE_REGISTER, + .parent = TYPE_DEVICE, +}; + +static void register_register_types(void) +{ + type_register_static(®ister_info); +} + +type_init(register_register_types) diff --git a/include/hw/register.h b/include/hw/register.h index 0c6f03d..6677dee 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -11,6 +11,7 @@ #ifndef REGISTER_H #define REGISTER_H +#include "hw/qdev-core.h" #include "exec/memory.h" typedef struct RegisterInfo RegisterInfo; @@ -101,6 +102,11 @@ struct RegisterAccessInfo { */ struct RegisterInfo { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + void *data; int data_size; @@ -119,6 +125,9 @@ struct RegisterInfo { MemoryRegion mem; }; +#define TYPE_REGISTER "qemu,register" +#define REGISTER(obj) OBJECT_CHECK(RegisterInfo, (obj), TYPE_REGISTER) + /** * write a value to a register, subject to its restrictions * @reg: register to write to @@ -144,6 +153,14 @@ uint64_t register_read(RegisterInfo *reg); void register_reset(RegisterInfo *reg); /** + * Initialize a register. GPIO's are setup as IOs to the specified device. + * Fast paths for eligible registers are enabled. + * @reg: Register to initialize + */ + +void register_init(RegisterInfo *reg); + +/** * Memory API MMIO write handler that will write to a Register API register. * _be for big endian variant and _le for little endian. * @opaque: RegisterInfo to write to