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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id m8-20020adfa3c8000000b0032d7fde2d3csm7990663wrb.79.2023.10.13.00.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:51:06 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org Cc: Emmanouil Pitsidianakis , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Bin Meng Subject: [RFC PATCH 39/75] hw/sd/sdhci.c: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:47:46 +0300 Message-Id: <9830d78710fbdfd12727e3777adfd585d99299c7.1697034504.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Emmanouil Pitsidianakis --- hw/sd/sdhci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 5564765a9b..5c641d24de 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -75,138 +75,138 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, static void sdhci_check_capareg(SDHCIState *s, Error **errp) { uint64_t msk = s->capareg; uint32_t val; bool y; switch (s->sd_spec_version) { case 4: val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); trace_sdhci_capareg("64-bit system bus (v4)", val); msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); trace_sdhci_capareg("UHS-II", val); msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); trace_sdhci_capareg("ADMA3", val); msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); - /* fallthrough */ + fallthrough; case 3: val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); trace_sdhci_capareg("async interrupt", val); msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); if (val) { error_setg(errp, "slot-type not supported"); return; } trace_sdhci_capareg("slot type", val); msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); if (val != 2) { val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); trace_sdhci_capareg("8-bit bus", val); } msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); trace_sdhci_capareg("bus speed mask", val); msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); trace_sdhci_capareg("driver strength mask", val); msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); trace_sdhci_capareg("timer re-tuning", val); msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); trace_sdhci_capareg("use SDR50 tuning", val); msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); trace_sdhci_capareg("re-tuning mode", val); msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); trace_sdhci_capareg("clock multiplier", val); msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); - /* fallthrough */ + fallthrough; case 2: /* default version */ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); trace_sdhci_capareg("ADMA2", val); msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); trace_sdhci_capareg("ADMA1", val); msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); trace_sdhci_capareg("64-bit system bus (v3)", val); msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); - /* fallthrough */ + fallthrough; case 1: y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { return; } msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); if (sdhci_check_capab_freq_range(s, "base", val, errp)) { return; } msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); if (val >= 3) { error_setg(errp, "block size can be 512, 1024 or 2048 only"); return; } trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); trace_sdhci_capareg("high speed", val); msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); trace_sdhci_capareg("SDMA", val); msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); trace_sdhci_capareg("suspend/resume", val); msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); trace_sdhci_capareg("3.3v", val); msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); trace_sdhci_capareg("3.0v", val); msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); trace_sdhci_capareg("1.8v", val); msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); break; default: error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); } if (msk) { qemu_log_mask(LOG_UNIMP, "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); } } @@ -1688,160 +1688,160 @@ static void usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { SDHCIState *s = SYSBUS_SDHCI(opaque); uint8_t hostctl1; uint32_t value = (uint32_t)val; switch (offset) { case USDHC_DLL_CTRL: case USDHC_TUNE_CTRL_STATUS: case USDHC_UNDOCUMENTED_REG27: case USDHC_TUNING_CTRL: case USDHC_WTMK_LVL: break; case USDHC_VENDOR_SPEC: s->vendor_spec = value; switch (s->vendor) { case SDHCI_VENDOR_IMX: if (value & USDHC_IMX_FRC_SDCLK_ON) { s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; } else { s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; } break; default: break; } break; case SDHC_HOSTCTL: /* * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) * * 7 6 5 4 3 2 1 0 * |-----------+--------+--------+-----------+----------+---------| * | Card | Card | Endian | DATA3 | Data | Led | * | Detect | Detect | Mode | as Card | Transfer | Control | * | Signal | Test | | Detection | Width | | * | Selection | Level | | Pin | | | * |-----------+--------+--------+-----------+----------+---------| * * and 0x29 * * 15 10 9 8 * |----------+------| * | Reserved | DMA | * | | Sel. | * | | | * |----------+------| * * and here's what SDCHI spec expects those offsets to be: * * 0x28 (Host Control Register) * * 7 6 5 4 3 2 1 0 * |--------+--------+----------+------+--------+----------+---------| * | Card | Card | Extended | DMA | High | Data | LED | * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | * | Signal | Test | Transfer | | Enable | Width | | * | Sel. | Level | Width | | | | | * |--------+--------+----------+------+--------+----------+---------| * * and 0x29 (Power Control Register) * * |----------------------------------| * | Power Control Register | * | | * | Description omitted, | * | since it has no analog in ESDHCI | * | | * |----------------------------------| * * Since offsets 0x2A and 0x2B should be compatible between * both IP specs we only need to reconcile least 16-bit of the * word we've been given. */ /* * First, save bits 7 6 and 0 since they are identical */ hostctl1 = value & (SDHC_CTRL_LED | SDHC_CTRL_CDTEST_INS | SDHC_CTRL_CDTEST_EN); /* * Second, split "Data Transfer Width" from bits 2 and 1 in to * bits 5 and 1 */ if (value & USDHC_CTRL_8BITBUS) { hostctl1 |= SDHC_CTRL_8BITBUS; } if (value & USDHC_CTRL_4BITBUS) { hostctl1 |= USDHC_CTRL_4BITBUS; } /* * Third, move DMA select from bits 9 and 8 to bits 4 and 3 */ hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); /* * Now place the corrected value into low 16-bit of the value * we are going to give standard SDHCI write function * * NOTE: This transformation should be the inverse of what can * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux * kernel */ value &= ~UINT16_MAX; value |= hostctl1; value |= (uint16_t)s->pwrcon << 8; sdhci_write(opaque, offset, value, size); break; case USDHC_MIX_CTRL: /* * So, when SD/MMC stack in Linux tries to write to "Transfer * Mode Register", ESDHC i.MX quirk code will translate it * into a write to ESDHC_MIX_CTRL, so we do the opposite in * order to get where we started * * Note that Auto CMD23 Enable bit is located in a wrong place * on i.MX, but since it is not used by QEMU we do not care. * * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) * here because it will result in a call to * sdhci_send_command(s) which we don't want. * */ s->trnmod = value & UINT16_MAX; break; case SDHC_TRNMOD: /* * Similar to above, but this time a write to "Command * Register" will be translated into a 4-byte write to * "Transfer Mode register" where lower 16-bit of value would * be set to zero. So what we do is fill those bits with * cached value from s->trnmod and let the SDHCI * infrastructure handle the rest */ sdhci_write(opaque, offset, val | s->trnmod, size); break; case SDHC_BLKSIZE: /* * ESDHCI does not implement "Host SDMA Buffer Boundary", and * Linux driver will try to zero this field out which will * break the rest of SDHCI emulation. * * Linux defaults to maximum possible setting (512K boundary) * and it seems to be the only option that i.MX IP implements, * so we artificially set it to that value. */ val |= 0x7 << 12; - /* FALLTHROUGH */ + fallthrough; default: sdhci_write(opaque, offset, val, size); break; } }