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[85.180.181.207]) by smtp.gmail.com with ESMTPSA id i10sm16160323wjd.15.2016.11.04.13.51.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Nov 2016 13:51:10 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Fri, 4 Nov 2016 21:50:03 +0100 Message-Id: <9aa71d05accc1355a28a0096309f3262b0006f1a.1478291230.git.atar4qemu@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Suggested-by: Richard Henderson Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target-sparc/cpu.h | 17 +++++++++++++++++ target-sparc/translate.c | 24 +++++++++++++++++++----- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index e0b2806..68e39bc 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -667,6 +667,11 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } +#else +static inline int cpu_supervisor_mode(CPUSPARCState *env1) +{ + return env1->psrs; +} #endif static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) @@ -733,6 +738,8 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_MMU_MASK 7 #define TB_FLAG_FPU_ENABLED (1 << 4) #define TB_FLAG_AM_ENABLED (1 << 5) +#define TB_FLAG_SUPER (1 << 6) +#define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, @@ -742,7 +749,17 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, *pc = env->pc; *cs_base = env->npc; flags = cpu_mmu_index(env, false); +#ifndef CONFIG_USER_ONLY + if (cpu_supervisor_mode(env)) { + flags |= TB_FLAG_SUPER; + } +#endif #ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY + if (cpu_hypervisor_mode(env)) { + flags |= TB_FLAG_HYPER; + } +#endif if (env->pstate & PS_AM) { flags |= TB_FLAG_AM_ENABLED; } diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 2205f89..0b0cde1 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -72,9 +72,16 @@ typedef struct DisasContext { target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ int is_br; int mem_idx; - int fpu_enabled; - int address_mask_32bit; - int singlestep; + bool fpu_enabled; + bool address_mask_32bit; + bool singlestep; +#ifndef CONFIG_USER_ONLY + bool supervisor; +#ifdef TARGET_SPARC64 + bool hypervisor; +#endif +#endif + uint32_t cc_op; /* current CC operation */ struct TranslationBlock *tb; sparc_def_t *def; @@ -283,10 +290,11 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) #define hypervisor(dc) 0 #endif #else -#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX) #ifdef TARGET_SPARC64 -#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX) +#define hypervisor(dc) (dc->hypervisor) +#define supervisor(dc) (dc->supervisor | dc->hypervisor) #else +#define supervisor(dc) (dc->supervisor) #endif #endif @@ -5710,9 +5718,15 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags); dc->singlestep = (cs->singlestep_enabled || singlestep); +#ifndef CONFIG_USER_ONLY + dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0; +#endif #ifdef TARGET_SPARC64 dc->fprs_dirty = 0; dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; +#ifndef CONFIG_USER_ONLY + dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0; +#endif #endif num_insns = 0;