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Fri, 18 Oct 2024 13:21:16 +0000 From: Aleksandar Rakic To: "qemu-devel@nongnu.org" CC: Djordje Todorovic , "cfu@mips.com" , "arikalo@gmail.com" , "peter.maydell@linaro.org" Subject: [PATCH v2 8/8] target/mips: Enable MSA ASE for mips64R2-generic Thread-Topic: [PATCH v2 8/8] target/mips: Enable MSA ASE for mips64R2-generic Thread-Index: AQHbIV6zG7r1NGRInEu1u+T5QtXCOw== Date: Fri, 18 Oct 2024 13:21:15 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: AM9PR09MB4851:EE_|GV2PR09MB5889:EE_ x-ms-office365-filtering-correlation-id: 85fbdbb6-98ad-458c-5a3c-08dcef77bec1 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|366016|1800799024|376014|38070700018; x-microsoft-antispam-message-info: =?iso-8859-1?q?je9M1hG++82TdDjl/A3/bmM4k7?= =?iso-8859-1?q?MqEGbzrG4hi9C5Jm/O3QshDOUytrKlSqVEFgg5I3AuJaGiHo9GSAm3+O4mmx?= =?iso-8859-1?q?7uPzEpFI1BICRu4DKBlYlFNrUqqPb+9UZOflSWQhFOPwsqYSvA9Q4ueUfkLi?= =?iso-8859-1?q?Kw+qdIOHAdJ9Liv7WG9fKB7pJM9drpUvOkpCvaT90SO8lazrcqcBmEZ84lKT?= =?iso-8859-1?q?l/f+GU9Mp4CKGMR5rfCVQCcFrMKIKa32T4a4niR+8LseZDri4hiRzmis/WsZ?= =?iso-8859-1?q?DGtbCHFFRjXe4DZG8I4wRyROLad5E3HWZzPaNvABJvhREAbjgBJVaO5e38UT?= =?iso-8859-1?q?tyG6iD24xpSjVa0UhI2MDo+oRYLj2mIwOf4s69rVnrmYU4l/JphVmLNbQgZR?= =?iso-8859-1?q?Rtbg8/JSKb+byzpnXon4ozinfsCzvpzD5wDfE0z3TBUOCkHZSArKAK88C1nD?= =?iso-8859-1?q?yOGZSQs/40x6HvSH8fzJB6xzk3kx1IE6wD1xA3YHi+/9afcamjKROb1mlqqG?= =?iso-8859-1?q?9QjZGIPatI5zqeEPKlaFCotb4R7rTC2Nm6xJwXQPfjWwHYZfDoyXL7Vxwhqq?= =?iso-8859-1?q?1knJC6mwrWmbcIZw+JniIdPO86mBAUW0x7JPUuSFLUBHiR/LACX45Tq1GmYw?= =?iso-8859-1?q?4UYs+n/CPEOp0nl+loa8D+PPTH8a9ZF7V9xYtcx1a9yewkeP7XrnksaERa04?= =?iso-8859-1?q?1XbvU0S8spASaKO/gCaOii3RScEsRDDSqv5+YE8XcP8sj41EWjlwfLXQCq9H?= =?iso-8859-1?q?C86+gtIkiZYDixcQ5YSyrh8FziNTtMNNW9SMyHVvYjjeqt090lndhn2vCDkn?= =?iso-8859-1?q?B60UbssjBAj+dRnKBg+x/nIiQW+xoOQEAKTgQULbIUrNRw8SfFH+CbEEEMmp?= =?iso-8859-1?q?b0Gcc/0Lqukim0/WkfF/2iLQUrHgnNO9DTHiVSUADRrLPgRlhATKSiUxCVBp?= =?iso-8859-1?q?JUD8kX4PYTMS6C0K6nWF2/rj4iDpLnkcloTbVOsoHdXbf8rWjIWVpCt9Lguq?= =?iso-8859-1?q?LW0ImWEslHNfD5NyuzZ86DaNnC8HA6kM/Y1wCdS2+bBwjtgZjhtXASE9Z3U7?= =?iso-8859-1?q?0I/Nvq6036V7Ek+VDnwzE4uCD5fn29iVxQxYEjoah41yAKdXaiD6msxeNoot?= =?iso-8859-1?q?n802cLjRFNPbm7kHX3B+ncsCjyglWm2AI8gaxGcpdUjhTITHaYgZVpQpl0QN?= =?iso-8859-1?q?ZVNfV235b/rqPzNjXlTV+KiHLqcYubKjLJif9lK+7AcvXLYCISAZ1DooiRL1?= =?iso-8859-1?q?EQb2tLgCin4TdNjorCs9Dk6tDWXubKyCYzOmiu2+jYW+fDexbCRAXJHYj+mZ?= =?iso-8859-1?q?d+BIHcYv0cU79BbX+EG07Pdocw4E++b1l/t+8ioh0AVkeHRfjps3DmT9Gdpn?= =?iso-8859-1?q?aMexSyF6o7RLEkosDGVTFI6vUt0kXPYuK/tzLkbypms8lGBG8FwNhEHf2jHq?= =?iso-8859-1?q?Gw?= x-forefront-antispam-report: CIP:255.255.255.255; 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envelope-from=aleksandar.rakic@htecgroup.com; helo=EUR02-VI1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable MSA ASE for mips64R2-generic CPU. Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f from https://github.com/MIPS/gnutools-qemu Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- target/mips/cpu-defs.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 19e2abac82..2b707cc5a7 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -678,7 +678,9 @@ const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | + (1 << CP0C3_VInt) | (1 << CP0C3_MSAP), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32,