From patchwork Mon Aug 5 12:14:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Grokhotkov X-Patchwork-Id: 11076671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6F3413AC for ; Mon, 5 Aug 2019 12:14:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B551D288E5 for ; Mon, 5 Aug 2019 12:14:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A98CF2876B; Mon, 5 Aug 2019 12:14:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C51B6287B9 for ; Mon, 5 Aug 2019 12:14:55 +0000 (UTC) Received: from localhost ([::1]:53400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hubt8-0007bW-7H for patchwork-qemu-devel@patchwork.kernel.org; Mon, 05 Aug 2019 08:14:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43263) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hubsT-0006iB-Lw for qemu-devel@nongnu.org; Mon, 05 Aug 2019 08:14:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hubsS-0004Ex-Ig for qemu-devel@nongnu.org; Mon, 05 Aug 2019 08:14:13 -0400 Received: from cnmail.espressif.com ([140.206.114.118]:15308) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hubsR-00045v-VA for qemu-devel@nongnu.org; Mon, 05 Aug 2019 08:14:12 -0400 Received: from [192.168.0.145] ([195.122.199.236]) by cnmail.espressif.com ((Espressif cloud mail system)) with ASMTP (SSL) id 201908052015300999; Mon, 05 Aug 2019 20:15:30 +0800 From: Ivan Grokhotkov Mime-Version: 1.0 (Mac OS X Mail 12.4 \(3445.104.11\)) Message-Id: Date: Mon, 5 Aug 2019 14:14:00 +0200 To: qemu-devel@nongnu.org X-Mailer: Apple Mail (2.3445.104.11) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 140.206.114.118 Subject: [Qemu-devel] [PATCH v2] target/riscv: don't overwrite priv_version and resetvec when realizing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP CPU-specific init functions (riscv_*_cpu_init) configure members of CPURISCVState, such as priv_version and resetvec. However riscv_cpu_realize unconditionally overwrites these members. The result is that some CPUs (such as CPU_SIFIVE_U34) are getting created with incorrect priv_version. Only set priv_version in riscv_cpu_realize if priv_spec property was set. Don't set resetvec in riscv_cpu_realize, rely on the init function to set it. Set default priv_version and resetvec in init functions where this was missing. Signed-off-by: Ivan Grokhotkov Reviewed-by: Alistair Francis Signed-off-by: Ivan Grokhotkov --- target/riscv/cpu.c | 12 +++++++----- target/riscv/cpu.h | 1 + 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8d07bd20a..8f3cb0c6bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,7 +110,7 @@ static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_DEFAULT); set_resetvec(env, DEFAULT_RSTVEC); } @@ -119,6 +119,8 @@ static void riscv_any_cpu_init(Object *obj) static void riscv_base32_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + set_priv_version(env, PRIV_VERSION_DEFAULT); + set_resetvec(env, DEFAULT_RSTVEC); /* We set this in the realise function */ set_misa(env, 0); } @@ -157,6 +159,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) static void riscv_base64_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + set_priv_version(env, PRIV_VERSION_DEFAULT); + set_resetvec(env, DEFAULT_RSTVEC); /* We set this in the realise function */ set_misa(env, 0); } @@ -316,7 +320,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) RISCVCPU *cpu = RISCV_CPU(dev); CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); - int priv_version = PRIV_VERSION_1_11_0; + int priv_version = PRIV_VERSION_DEFAULT; target_ulong target_misa = 0; Error *local_err = NULL; @@ -339,11 +343,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.priv_spec); return; } + set_priv_version(env, priv_version); } - set_priv_version(env, priv_version); - set_resetvec(env, DEFAULT_RSTVEC); - if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0adb307f32..88a52a1c8c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ enum { #define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 +#define PRIV_VERSION_DEFAULT PRIV_VERSION_1_11_0 #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1