Message ID | CA+tJHD4Fdv54_u9vffu9tNuor4Tu_Ld-eYZkLRmTxi=X2wknnw@mail.gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2] riscv: Make semihosting configurable for all privilege modes | expand |
On Sat, 13 Aug 2022 at 00:23, Furquan Shaikh <furquan@rivosinc.com> wrote: > > Unlike ARM, RISC-V does not define a separate breakpoint type for > semihosting. Instead, it is entirely ABI. Thus, we need an option > to allow users to configure what the ebreak behavior should be for > different privilege levels - M, S, U, VS, VU. As per the RISC-V > privilege specification[1], ebreak traps into the execution > environment. However, RISC-V debug specification[2] provides > ebreak{m,s,u,vs,vu} configuration bits to allow ebreak behavior to > be configured to trap into debug mode instead. This change adds > settable properties for RISC-V CPUs - `ebreakm`, `ebreaks`, `ebreaku`, > `ebreakvs` and `ebreakvu` to allow user to configure whether qemu > should treat ebreak as semihosting traps or trap according to the > privilege specification. > > [1] https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-privileged.pdf > [2] https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Signed-off-by: Furquan Shaikh <furquan@rivosinc.com> > --- As per the discussion thread on the v1 patch, I don't think this is the right way to solve the underlying problem you ran into. We should fix that with a generic "allow semihosting calls from userspace" option. thanks -- PMM
diff --git a/qemu-options.hx b/qemu-options.hx index 3f23a42fa8..1e2e153946 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4635,7 +4635,9 @@ SRST open/read/write/seek/select. Tensilica baremetal libc for ISS and linux platform "sim" use this interface. - On RISC-V this implements the standard semihosting API, version 0.2. + On RISC-V this implements the standard semihosting API, version 0.2. See + the ebreak{m,s,u,vs,vu} CPU properties to control which modes treat + breakpoints as semihosting calls. ``target=native|gdb|auto`` Defines where the semihosting calls will be addressed, to QEMU diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac6f82ebd0..082194652b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -953,6 +953,14 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), + + /* Debug spec */ + DEFINE_PROP_BOOL("ebreakm", RISCVCPU, cfg.ebreakm, true), + DEFINE_PROP_BOOL("ebreaks", RISCVCPU, cfg.ebreaks, false), + DEFINE_PROP_BOOL("ebreaku", RISCVCPU, cfg.ebreaku, false), + DEFINE_PROP_BOOL("ebreakvs", RISCVCPU, cfg.ebreakvs, false), + DEFINE_PROP_BOOL("ebreakvu", RISCVCPU, cfg.ebreakvu, false), + DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc055a..eee8e487a6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -454,6 +454,13 @@ struct RISCVCPUConfig { bool epmp; bool aia; bool debug; + + /* Debug spec */ + bool ebreakm; + bool ebreaks; + bool ebreaku; + bool ebreakvs; + bool ebreakvu; uint64_t resetvec; bool short_isa_string; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 59b3680b1b..be09abbe27 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1314,6 +1314,30 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } + +static bool semihosting_enabled(RISCVCPU *cpu) +{ + CPURISCVState *env = &cpu->env; + + switch (env->priv) { + case PRV_M: + return cpu->cfg.ebreakm; + case PRV_S: + if (riscv_cpu_virt_enabled(env)) { + return cpu->cfg.ebreakvs; + } else { + return cpu->cfg.ebreaks; + } + case PRV_U: + if (riscv_cpu_virt_enabled(env)) { + return cpu->cfg.ebreakvu; + } else { + return cpu->cfg.ebreaku; + } + } + + return false; +} #endif /* !CONFIG_USER_ONLY */