Message ID | CAHNT7NtxixSEz5J+5m1QufA_R+=oTuU_Avp2-X8_uoCpxkkQyw@mail.gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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X-Received-From: 2607:f8b0:4003:c0f::235 Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> X-Virus-Scanned: ClamAV using ClamSMTP |
diff --git a/qapi-schema.json b/qapi-schema.json index 42d91f3..79a2f62 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -410,6 +410,8 @@ # An enumeration of cpu types that enable additional information during # @query-cpus. # +# @riscv: since 2.12 +# # Since: 2.6 ## { 'enum': 'CpuInfoArch',