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[74.199.53.164]) by smtp.gmail.com with ESMTPSA id 204sm1314069itz.29.2017.04.24.20.20.38 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 24 Apr 2017 20:20:38 -0700 (PDT) Mime-Version: 1.0 (Apple Message framework v753.1) Message-Id: From: G 3 Date: Mon, 24 Apr 2017 23:20:36 -0400 To: Peter Maydell X-Mailer: Apple Mail (2.753.1) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::241 Subject: [Qemu-devel] [PATCH 4/9] Add risu_reginfo_ppc.h file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org qemu-devel" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the risu_reginfo_ppc.h file. It defines the reginfo structure. Signed-off-by: John Arbuckle --- risu_reginfo_ppc.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 risu_reginfo_ppc.h + */ +}; + +#endif /* RISU_REGINFO_PPC_H */ diff --git a/risu_reginfo_ppc.h b/risu_reginfo_ppc.h new file mode 100644 index 0000000..c3b342d --- /dev/null +++ b/risu_reginfo_ppc.h @@ -0,0 +1,32 @@ +/****************************************** + * File: risu_reginfo_ppc.h + * Description: 32 bit powerpc registers + * Date: 3-26-2017 + ******************************************/ + +#ifndef RISU_REGINFO_PPC_H +#define RISU_REGINFO_PPC_H + +struct reginfo +{ + uint32_t faulting_insn; + uint32_t previous_instruction; /* The instruction before the faulting instruction */ + uint32_t second_previous_instruction; /* The second instruction before the faulting instruction */ + + /************** User Model UISA *********************************/ + + uint32_t gpr[32]; /* General Purpose Registers */ + double fpr[32]; /* Floating-point Registers */ + uint32_t cr; /* Condition Register */ + uint32_t fpscr; /* Floating-point Status and Control Register */ + uint32_t xer; /* Fixed-point Exception Register */ + uint32_t lr; /* Link Register */ + uint32_t ctr; /* Count Register */ + + /* + * Since we can't test any registers in the Supervisor Model, they are not + * included.