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Fri, 27 Sep 2024 12:15:49 +0000 From: Aleksandar Rakic To: "qemu-devel@nongnu.org" CC: Djordje Todorovic , "cfu@mips.com" Subject: [PATCH 7/8] target/mips: Enable MSA ASE for mips32r6-generic Thread-Topic: [PATCH 7/8] target/mips: Enable MSA ASE for mips32r6-generic Thread-Index: AQHbENaeasAshFkTbkmP5utGs9GItg== Date: Fri, 27 Sep 2024 12:15:49 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PA4PR09MB4864:EE_|DB4PR09MB6621:EE_ x-ms-office365-filtering-correlation-id: 9972e7dc-edd4-474e-1a34-08dcdeee1f97 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|376014|1800799024|366016|38070700018; x-microsoft-antispam-message-info: =?iso-8859-1?q?uzh60UiUyqZOaC9DuF85Mkr9PW?= =?iso-8859-1?q?EoY+GWfbUxDxe4ttuIegFk0G+qduBWuH6zm6+2uD3+YTkutYV0RbzhIf6IOK?= =?iso-8859-1?q?nX4E4vqg1QJr/2EaxO8p6oL5k/IagnTcFrSZrQpYQZqxxsWZvKoqSlHHN8Of?= =?iso-8859-1?q?c0Qw1+HGiw8kdKj2HVYRTWkrpZiZjYBycJqt09a2rVpMo7whm1Nm6nmy/0Bq?= =?iso-8859-1?q?pZ0oiw4EiL7mLmdFePMhFUiFhjk9Dhm0/laKMtJXG2drTNMhbuU18pkbRvq3?= =?iso-8859-1?q?DLKSQxJLTEsVd7m1LkL7Z4DWFVe7I9ODhkaLV44cy3T/67zplp/au3MsKWw4?= =?iso-8859-1?q?rlBVuKp90JFoNlZACx7qQyM9ecp3MbNEpmSYQjjUXQ/PpYPGTg4eJiYw0I2w?= =?iso-8859-1?q?Fzp7mCv2tlYa6x1MGqEcKSLuSqScjRGz+OSwzDYENMAE2sgVBoshrkwC1jYs?= =?iso-8859-1?q?yxY/HXHZuRaDpGMCg7ToSFtK1RZODdVB4pb8TqV8Kw/5zAirRWAoBJ+LVcdI?= =?iso-8859-1?q?i69alM7gmbhyBwvWisTGicniyhedLlw+muRebkN0kOJhNVGiO3F3tzg0GRCn?= =?iso-8859-1?q?/Rx1/ZhWDtWHxNZHhe95ntiZvt64liGe4DFw9WskEz2XIr5BLopbVQru1Iet?= =?iso-8859-1?q?pcTqb+Pe4XI3oSLTTSK7u0lHIDH2KvPTZpJmnFUBjUNwQ2ovLSOBopwq5XNY?= =?iso-8859-1?q?uUOQ/AoWQ5QXX87cl21UgMJpFmCCNlramBU6fZq+UaYxdLvIqEzhzFoKEWbs?= =?iso-8859-1?q?Uz+wwBPTDgeuCs0SAYjH6DnsMnyIiehd66HSUxwlorLBoR5iJbQuZfpI4psn?= =?iso-8859-1?q?VHfuIUlvrRWPUTcyW2n12GW8qNGoenxBVxDELIPg9RMCWbz0lMH0UKV/Nb0O?= =?iso-8859-1?q?NdRnr4P7KSHBZ4LZhUxnb/wUjcnEwmlEgQClt5Z7XUo3etTnVHBlsJSsmbOq?= =?iso-8859-1?q?h7sKTSKw87W+seKBsWc3oWFEDPLx9/L0Dx1+LEGg5GnG8KtMVvtzi2bu6rQU?= =?iso-8859-1?q?qlksHuTfLS0whwhBCwIgbMhP9pfnyAlYsoX83M/iSUCE556jUfqXvkxGZ51N?= =?iso-8859-1?q?461PJ5pmBCTvocZAY/y6lRlfBxOaFgcOz4lnSOS7gnBH1fkPJMlzIeO35Ekx?= =?iso-8859-1?q?GKzw8mSUPe5OTQcr8o8qvnw+bhtBU/NAMCAmbg5T1CWsMdr3mWzun/PcUh49?= =?iso-8859-1?q?jS/B1MBISryu9hXhVGI75Ct6hFjeldNGn0Xv/2bZC0xxsfHg8gOKGvlLX7vP?= =?iso-8859-1?q?uBuZ16fnQuXsD5vWloAG1Fvixe/CXonEb+RFPMp0mQoYCzSsuLkEIJdeApmX?= =?iso-8859-1?q?A7OJOOaxefrnJ7J7lQstibiKpnUwFut641ndfF5GRemd0zx5v6EqnOvHghgk?= =?iso-8859-1?q?ITNkqnRezAse5yaPvL67nkifQmdxl4g52xVdfou45iJ0a2N0VwL3UCmDQ9lB?= =?iso-8859-1?q?PmmBv+4OEj9waYRExKWhvzbA=3D=3D?= x-forefront-antispam-report: CIP:255.255.255.255; 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envelope-from=aleksandar.rakic@htecgroup.com; helo=EUR05-DB8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 27 Sep 2024 09:25:49 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable MSA ASE for mips32r6-generic CPU. Cherry-picked 0186e83a0613e90aff6d4c12c91cdb080d695d37 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Aleksandar Markovic Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic --- target/mips/cpu-defs.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 9428ece220..19e2abac82 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -478,14 +478,15 @@ const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1U << CP0C3_M), .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1U << CP0C4_M), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | - (1 << CP0C5_UFE), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, @@ -499,6 +500,7 @@ const mips_def_t mips_defs[] = (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .MSAIR = 0x03 << MSAIR_ProcID, .SEGBITS = 32, .PABITS = 32, .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,