From patchwork Tue Sep 3 10:28:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13788562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D2B8CD13CF for ; Tue, 3 Sep 2024 11:38:30 +0000 (UTC) Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1slQvh-0003Eu-KK; Tue, 03 Sep 2024 06:38:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1slQvA-0003E4-0b for qemu-devel@nongnu.org; Tue, 03 Sep 2024 06:38:06 -0400 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1slQus-00019B-0z for qemu-devel@nongnu.org; Tue, 03 Sep 2024 06:37:59 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 2551C5C578C; Tue, 3 Sep 2024 10:28:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD318C4CEC8; Tue, 3 Sep 2024 10:28:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725359317; bh=RYb6s9O54ICo2BwWX7TxXxyUNqLwOuWQoGQsY7xAbag=; h=Date:From:To:Cc:Subject:From; b=fq5pGlQZXeskeTS60x9DkSiSkMkNhjKg6R9lxfYY0SMiSDo+gbLX6SsKFKgzaZiE/ gd4usIft49PWuOSYYHp8z8qWCwasjFmk578YDgWdD/GO9AXLVjlUI7ayn7HbGgHZYu 851F/n7gv9X9SBkOu3VpJ1o4qUPdiwSSmyLXhtDpBC7UmRa+PFOAnSSxy8+4R8m216 0OUcfuoDG7vqJj313htAI65oI1zzV8dI4XNjYLw4XgqcHpVLPTTGE3MBvCcoHQ3L7c CKBXahHst5IoN95f1VRh14L5H9oFpofEbkwqOykAMl+8V8hQO+MvVKacUAzR6x9hMC d1+nypREYKmSA== Date: Tue, 3 Sep 2024 12:28:33 +0200 From: Helge Deller To: Richard Henderson , qemu-devel@nongnu.org, Philippe =?iso-8859-15?q?Mathieu-Daud=E9?= Cc: linux-parisc@vger.kernel.org, Guenter Roeck Subject: [PATCH] target/hppa: Fix PSW V-bit packaging in cpu_hppa_get for hppa64 Message-ID: MIME-Version: 1.0 Content-Disposition: inline Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -72 X-Spam_score: -7.3 X-Spam_bar: ------- X-Spam_report: (-7.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.142, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While adding hppa64 support, the psw_v variable got extended from 32 to 64 bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt processing, check bit 31 instead the 63th (sign) bit. This fixes a hard to find Linux kernel boot issue where the loss of the PSW-V bit due to an ITLB interruption in the middle of a series of ds/addc instructions (from the divU milicode library) generated the wrong division result and thus triggered a Linux kernel crash. Link: https://lore.kernel.org/lkml/718b8afe-222f-4b3a-96d3-93af0e4ceff1@roeck-us.net/ Reported-by: Guenter Roeck Signed-off-by: Helge Deller Fixes: 931adff31478 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64") Tested-by: Guenter Roeck Reviewed-by: Richard Henderson diff --git a/target/hppa/helper.c b/target/hppa/helper.c index b79ddd8184..d4b1a3cd5a 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -53,7 +53,7 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) } psw |= env->psw_n * PSW_N; - psw |= (env->psw_v < 0) * PSW_V; + psw |= ((env->psw_v >> 31) & 1) * PSW_V; psw |= env->psw | env->psw_xb; return psw;