@@ -235,15 +235,39 @@ static const TCGCPUOps hppa_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
+static void hppa_cpu_reset_hold(Object *obj, ResetType type)
+{
+ HPPACPU *cpu = HPPA_CPU(obj);
+ HPPACPUClass *scc = HPPA_CPU_GET_CLASS(cpu);
+ CPUHPPAState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+
+ if (scc->parent_phases.hold) {
+ scc->parent_phases.hold(obj, type);
+ }
+
+ memset(env, 0, sizeof(*env));
+
+ cpu_set_pc(cs, 0xf0000004);
+ env->psw = PSW_Q;
+
+ cs->exception_index = -1;
+ cs->halted = 0;
+}
+
static void hppa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, hppa_cpu_realizefn,
&acc->parent_realize);
+ resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL,
+ &acc->parent_phases);
+
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
cc->mmu_index = hppa_cpu_mmu_index;
@@ -281,6 +281,7 @@ struct ArchCPU {
/**
* HPPACPUClass:
* @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* An HPPA CPU model.
*/
@@ -288,6 +289,7 @@ struct HPPACPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
};
#include "exec/cpu-all.h"
Add the missing CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf0000004. Signed-off-by: Helge Deller <deller@gmx.de>