[v1,14/15] target/riscv: Only support little endian guests

Commit Message

Alistair Francis April 26, 2020, 4:19 p.m. UTC

Signed-off-by: Alistair Francis <[e-mail]>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 438d0a61ee..04f3471f2e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -858,6 +858,8 @@  static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
     /* We only support 64-bit VSXL */
     *val = set_field(*val, HSTATUS_VSXL, 2);
 #endif
+    /* We only support little endian */
+    *val = set_field(*val, HSTATUS_VSBE, 0);
     return 0;
 }
 
@@ -869,6 +871,9 @@  static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
     }
 #endif
+    if (get_field(val, HSTATUS_VSBE) != 0) {
+        qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+    }
     return 0;
 }