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16 Dec 2020 10:06:32 -0800 IronPort-SDR: 5TU1A5WCHP/OQaRHhRusflQPP/n+L7PtCRFzgSdlyFIsHroiegrtJBU0Tbty1E8Z1OB5aXp3jU +knC/X7N2063CQNxoLcqGxr3iq8IU9YO8IuW8KmGA5lzbXwqwQNCY19ZDF87+sceBxoh1rTvFz wjCbN/noCFq/OhlaUbTFVdSExhOTRCeooy00nmcq4XOaPcNOhhGAsCbW4Djds7MTX/FAnup4mN f903vFwJ2Y0pvIJID0/0VMXrJczlbuObllmY6F7Uy4sjAYoOygrD1OvAhxdBf7ZyUpMu3PYd0R mC8= WDCIronportException: Internal Received: from 1996l72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.67]) by uls-op-cesaip02.wdc.com with ESMTP; 16 Dec 2020 10:22:57 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks Date: Wed, 16 Dec 2020 10:22:56 -0800 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=612374860=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Tested-by: Bin Meng --- target/riscv/cpu.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6f032122..47b738c314 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,10 +240,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); -#ifdef TARGET_RISCV32 - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); -#endif + if (riscv_cpu_is_32bit(env)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", + (target_ulong)(env->mstatus >> 32)); + } if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", @@ -356,11 +356,12 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { -#if defined(TARGET_RISCV32) - info->print_insn = print_insn_riscv32; -#elif defined(TARGET_RISCV64) - info->print_insn = print_insn_riscv64; -#endif + RISCVCPU *cpu = RISCV_CPU(s); + if (riscv_cpu_is_32bit(&cpu->env)) { + info->print_insn = print_insn_riscv32; + } else { + info->print_insn = print_insn_riscv64; + } } static void riscv_cpu_realize(DeviceState *dev, Error **errp)