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[37.6.0.26]) by smtp.gmail.com with ESMTPSA id a10-20020a05600c224a00b003fe23b10fdfsm1798183wmm.36.2023.10.13.00.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:59:56 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Subject: [RFC PATCH v2 67/78] hw/pci-host/pnv_phb3.c: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:57:34 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/pci-host/pnv_phb3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index c5e58f4086..6a805d3900 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -470,121 +470,121 @@ static void pnv_phb3_update_all_msi_regions(PnvPHB3 *phb) void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) { PnvPHB3 *phb = opaque; bool changed; /* Special case configuration data */ if ((off & 0xfffc) == PHB_CONFIG_DATA) { pnv_phb3_config_write(phb, off & 0x3, size, val); return; } /* Other registers are 64-bit only */ if (size != 8 || off & 0x7) { phb3_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d", off, size); return; } /* Handle masking & filtering */ switch (off) { case PHB_M64_UPPER_BITS: val &= 0xfffc000000000000ull; break; case PHB_Q_DMA_R: /* * This is enough logic to make SW happy but we aren't actually * quiescing the DMAs */ if (val & PHB_Q_DMA_R_AUTORESET) { val = 0; } else { val &= PHB_Q_DMA_R_QUIESCE_DMA; } break; /* LEM stuff */ case PHB_LEM_FIR_AND_MASK: phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val; return; case PHB_LEM_FIR_OR_MASK: phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val; return; case PHB_LEM_ERROR_AND_MASK: phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val; return; case PHB_LEM_ERROR_OR_MASK: phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val; return; case PHB_LEM_WOF: val = 0; break; } /* Record whether it changed */ changed = phb->regs[off >> 3] != val; /* Store in register cache first */ phb->regs[off >> 3] = val; /* Handle side effects */ switch (off) { case PHB_PHB3_CONFIG: if (changed) { pnv_phb3_update_all_msi_regions(phb); } - /* fall through */ + fallthrough; case PHB_M32_BASE_ADDR: case PHB_M32_BASE_MASK: case PHB_M32_START_ADDR: if (changed) { pnv_phb3_check_m32(phb); } break; case PHB_M64_UPPER_BITS: if (changed) { pnv_phb3_check_all_m64s(phb); } break; case PHB_LSI_SOURCE_ID: if (changed) { pnv_phb3_lsi_src_id_write(phb, val); } break; /* IODA table accesses */ case PHB_IODA_DATA0: pnv_phb3_ioda_write(phb, val); break; /* RTC invalidation */ case PHB_RTC_INVALIDATE: pnv_phb3_rtc_invalidate(phb, val); break; /* FFI request */ case PHB_FFI_REQUEST: pnv_phb3_msi_ffi(&phb->msis, val); break; /* Silent simple writes */ case PHB_CONFIG_ADDRESS: case PHB_IODA_ADDR: case PHB_TCE_KILL: case PHB_TCE_SPEC_CTL: case PHB_PEST_BAR: case PHB_PELTV_BAR: case PHB_RTT_BAR: case PHB_RBA_BAR: case PHB_IVT_BAR: case PHB_FFI_LOCK: case PHB_LEM_FIR_ACCUM: case PHB_LEM_ERROR_MASK: case PHB_LEM_ACTION0: case PHB_LEM_ACTION1: break; /* Noise on anything else */ default: qemu_log_mask(LOG_UNIMP, "phb3: reg_write 0x%"PRIx64"=%"PRIx64"\n", off, val); } }