diff mbox series

[v2,14/27] target/ricsv: Flush the TLB on virtulisation mode changes

Message ID ad856f89f6f0be30be0eb28560eb85f1970e6756.1572045716.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V Hypervisor Extension v0.4 | expand

Commit Message

Alistair Francis Oct. 25, 2019, 11:23 p.m. UTC
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/cpu_helper.c | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bb4557df16..637e05996a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -200,6 +200,11 @@  void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
         return;
     }
 
+    /* Flush the TLB on all virt mode changes. */
+    if (get_field(env->virt, VIRT_ONOFF) != enable) {
+        tlb_flush(env_cpu(env));
+    }
+
     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
 }