From patchwork Mon Mar 25 11:01:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C93013B5 for ; Mon, 25 Mar 2019 11:14:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5732C28479 for ; Mon, 25 Mar 2019 11:14:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A7AC284F1; Mon, 25 Mar 2019 11:14:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DE87028479 for ; Mon, 25 Mar 2019 11:14:30 +0000 (UTC) Received: from localhost ([127.0.0.1]:40663 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8NYj-0006wZ-Ka for patchwork-qemu-devel@patchwork.kernel.org; Mon, 25 Mar 2019 07:14:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:58867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8NNh-0005Vp-NK for qemu-devel@nongnu.org; Mon, 25 Mar 2019 07:03:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h8NNg-00087d-K0 for qemu-devel@nongnu.org; Mon, 25 Mar 2019 07:03:05 -0400 Received: from greensocs.com ([193.104.36.180]:38406) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8NNc-0007uj-8I; Mon, 25 Mar 2019 07:03:01 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 7F4057D78AF; Mon, 25 Mar 2019 12:02:36 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511756; bh=cHW197nSVdJdU8mrnmNppk6kPW0LZpeckZV4M1rzKSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=iMsmu9kREy11cFz1q4qYLycqCMGrVIcaAL50u6ZUTZpyDxKxtmLxUurfTzQHwjdr9 QtBBjhrVBDQMzCseJYcr8k6cXe0tBuZhWMXejNRT5TgWVO23lfn171G4j77x0mjASO 3XmP+S93ZqLLqeCAhQgOP8q4Lvb/qipXo7LiWxhE= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=3dFuaE6J; dkim=pass (1024-bit key) header.d=greensocs.com header.b=b9ti8lX+ Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iw8qMQxap1Ud; Mon, 25 Mar 2019 12:02:35 +0100 (CET) Received: by greensocs.com (Postfix, from userid 998) id 500597D78B6; Mon, 25 Mar 2019 12:02:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511754; bh=cHW197nSVdJdU8mrnmNppk6kPW0LZpeckZV4M1rzKSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=3dFuaE6JK0FQkbEHN+eADqTGGM986siG1DRmx50h+eTuP+6eofiTILtMmgt0HpIAO jFVPbsw0OzepB6zyJH6P5UCarulWcfKiSbgkGO7TZih4dJo7YOswAYQVmO2g7BbMzh Sq+uSdjH7QUcZA9wc3anUO6GHcZvyd2ym2iliTws= Received: from kouign-amann.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: damien.hedde@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 6AE907D789E; Mon, 25 Mar 2019 12:02:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511753; bh=cHW197nSVdJdU8mrnmNppk6kPW0LZpeckZV4M1rzKSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=b9ti8lX+1jB/p50Qd+i9TV7PY51AjPUyWodE4uKylVctOvIokpeZfQjtSrgebl7I2 eOFE4wTt3/ajXzPw5FCia4PYOCO8SIt2FWpPKrsSWcR9ESOxcy2loX51iWt4LH9Kle tjhZHbNBphnIyJkfAkENNNq+clqokFhW0zuF68+E= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:59 +0100 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add two gpio outputs to control the uart resets. Signed-off-by: Damien Hedde --- hw/misc/zynq_slcr.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 47f43e1d8d..5aa8f55b45 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -96,6 +96,10 @@ REG32(SPI_RST_CTRL, 0x21c) REG32(CAN_RST_CTRL, 0x220) REG32(I2C_RST_CTRL, 0x224) REG32(UART_RST_CTRL, 0x228) + FIELD(UART_RST_CTRL, UART0_CPU1X_RST, 0, 1) + FIELD(UART_RST_CTRL, UART1_CPU1X_RST, 1, 1) + FIELD(UART_RST_CTRL, UART0_REF_RST, 2, 1) + FIELD(UART_RST_CTRL, UART1_REF_RST, 3, 1) REG32(GPIO_RST_CTRL, 0x22c) REG32(LQSPI_RST_CTRL, 0x230) REG32(SMC_RST_CTRL, 0x234) @@ -178,8 +182,14 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + qemu_irq uart0_rst; + qemu_irq uart1_rst; } ZynqSLCRState; +#define ZYNQ_SLCR_REGFIELD_TO_OUT(state, irq, reg, field) \ + qemu_set_irq((state)->irq, ARRAY_FIELD_EX32((state)->regs, reg, field) != 0) + static void zynq_slcr_reset_init(Object *obj, bool cold) { ZynqSLCRState *s = ZYNQ_SLCR(obj); @@ -276,6 +286,18 @@ static void zynq_slcr_reset_init(Object *obj, bool cold) s->regs[R_DDRIOB + 12] = 0x00000021; } +static void zynq_slcr_compute_uart_reset(ZynqSLCRState *s) +{ + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart0_rst, UART_RST_CTRL, UART0_REF_RST); + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart1_rst, UART_RST_CTRL, UART1_REF_RST); +} + +static void zynq_slcr_reset_hold(Object *obj) +{ + ZynqSLCRState *s = ZYNQ_SLCR(obj); + + zynq_slcr_compute_uart_reset(s); +} static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { @@ -416,6 +438,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case R_UART_RST_CTRL: + zynq_slcr_compute_uart_reset(s); + break; } } @@ -432,6 +457,9 @@ static void zynq_slcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", ZYNQ_SLCR_MMIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qdev_init_gpio_out_named(DEVICE(obj), &s->uart0_rst, "uart0_rst", 1); + qdev_init_gpio_out_named(DEVICE(obj), &s->uart1_rst, "uart1_rst", 1); } static const VMStateDescription vmstate_zynq_slcr = { @@ -450,6 +478,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_zynq_slcr; dc->reset_phases.init = zynq_slcr_reset_init; + dc->reset_phases.hold = zynq_slcr_reset_hold; } static const TypeInfo zynq_slcr_info = {