From patchwork Thu Oct 19 21:08:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 10018313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7582360215 for ; Thu, 19 Oct 2017 21:09:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 683F0286BD for ; Thu, 19 Oct 2017 21:09:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B838286C1; Thu, 19 Oct 2017 21:09:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C9AE6286C4 for ; Thu, 19 Oct 2017 21:09:17 +0000 (UTC) Received: from localhost ([::1]:51247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e5I44-00058E-Sb for patchwork-qemu-devel@patchwork.kernel.org; Thu, 19 Oct 2017 17:09:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e5I3R-00056l-Vq for qemu-devel@nongnu.org; Thu, 19 Oct 2017 17:08:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e5I3Q-0007j3-P8 for qemu-devel@nongnu.org; Thu, 19 Oct 2017 17:08:37 -0400 Received: from mail.kernel.org ([198.145.29.99]:41768) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e5I3K-0007eu-2w; Thu, 19 Oct 2017 17:08:30 -0400 Received: from [10.149.184.130] (162-198-228-33.lightspeed.wlfrct.sbcglobal.net [162.198.228.33]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 94DC82191C; Thu, 19 Oct 2017 21:08:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 94DC82191C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=sstabellini@kernel.org Date: Thu, 19 Oct 2017 14:08:24 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@sstabellini-ThinkPad-X260 To: Peter Maydell In-Reply-To: Message-ID: References: User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.99 Subject: Re: [Qemu-devel] [PATCH] don't hardcode EL1 in extended_addresses_enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , QEMU Developers , qemu-arm Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On Thu, 19 Oct 2017, Peter Maydell wrote: > On 18 October 2017 at 23:41, Stefano Stabellini wrote: > > extended_addresses_enabled calls arm_el_is_aa64, hardcoding exception > > level 1. Instead, retrieve the current el calling arm_current_el. > > > > Signed-off-by: Stefano Stabellini > > > > diff --git a/target/arm/internals.h b/target/arm/internals.h > > index 1f6efef..63507d9 100644 > > --- a/target/arm/internals.h > > +++ b/target/arm/internals.h > > @@ -187,7 +187,7 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) > > static inline bool extended_addresses_enabled(CPUARMState *env) > > { > > TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; > > - return arm_el_is_aa64(env, 1) || > > + return arm_el_is_aa64(env, arm_current_el(env)) || > > (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); > > } > > Hmm. The current code was definitely written under a "aarch64 > only supports EL0 and EL1" assumption, but I'm not sure > this change is entirely correct. > > We use this function in 3 places: > > * identifying whether to flush TLBs on CONTEXTIDR writes > -- using current EL seems like the right thing (but I'm not > sure -- perhaps we should pass in the S/NS from which > version of the 32-bit banked register is being updated > rather than using arm_is_secure(env) ???) > * choosing a PAR format for ATS operations > -- using the current EL is closer to correct that what we > have now. There are cases for a 32-bit CPU in Hyp mode that > this code mishandles, but we don't support that yet. > * choosing an FSR value when taking a breakpoint or watchpoint trap > -- here what we want the function to mean is "what is the > FSR format for the EL we're about to take this debug > exception to", which isn't necessarily the answer for the > current EL (consider 32 bit EL0 under a 64-bit EL1) > > So this change will fix the PAR format for ATS operations > made at AArch64 EL2 when EL1 is AArch32, but it will break > the FSR format for breakpoints/watchpoints hit at AArch32 EL0 > and taken to AArch64 EL1, I think. > > We probably need to separate out these uses to not all try > to use the same function, and clarify what they're checking. What if we do use a single extended_addresses_enabled function, but we pass the EL to check? I think it makes sense, but please check the changes below, especially the ones to arm_debug_excp_handler. What do you think? diff --git a/target/arm/helper.c b/target/arm/helper.c index 96113fe..2298428 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -500,7 +500,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMCPU *cpu = arm_env_get_cpu(env); if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { + && !extended_addresses_enabled(env, arm_current_el(env))) { /* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. @@ -2162,7 +2162,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); - if (extended_addresses_enabled(env)) { + if (extended_addresses_enabled(env, arm_current_el(env))) { /* fsr is a DFSR/IFSR value for the long descriptor * translation table format, but with WnR always clear. * Convert it to a 64-bit PAR. diff --git a/target/arm/internals.h b/target/arm/internals.h index 43106a2..6792df2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -217,10 +217,10 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) * This is always the case if our translation regime is 64 bit, * but depends on TTBCR.EAE for 32 bit. */ -static inline bool extended_addresses_enabled(CPUARMState *env) +static inline bool extended_addresses_enabled(CPUARMState *env, unsigned int el) { - TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; - return arm_el_is_aa64(env, 1) || + TCR *tcr = &env->cp15.tcr_el[el]; + return arm_el_is_aa64(env, el) || (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 3914145..4f46eb8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1378,7 +1378,7 @@ void arm_debug_excp_handler(CPUState *cs) cs->watchpoint_hit = NULL; - if (extended_addresses_enabled(env)) { + if (extended_addresses_enabled(env, arm_debug_target_el(env))) { env->exception.fsr = (1 << 9) | 0x22; } else { env->exception.fsr = 0x2; @@ -1402,7 +1402,7 @@ void arm_debug_excp_handler(CPUState *cs) return; } - if (extended_addresses_enabled(env)) { + if (extended_addresses_enabled(env, arm_debug_target_el(env))) { env->exception.fsr = (1 << 9) | 0x22; } else { env->exception.fsr = 0x2;