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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id v10-20020a5d678a000000b0032d9f32b96csm569185wru.62.2023.10.13.01.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 01:48:00 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [RFC PATCH v3 27/78] target/riscv: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 11:45:55 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 2 +- target/riscv/insn_trans/trans_rvzce.c.inc | 22 +++++++++++----------- target/riscv/translate.c | 4 ++-- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 25cb60558a..98dd2e3cf6 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -122,7 +122,7 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl, case TCG_COND_LTU: invert = true; - /* fallthrough */ + fallthrough; case TCG_COND_GEU: { TCGv tmp = tcg_temp_new(); diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index 2d992e14c4..f0bcbb4f72 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -125,37 +125,37 @@ static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist) case 15: reg_bitmap |= 1 << (X_Sn + 11) ; reg_bitmap |= 1 << (X_Sn + 10) ; - /* FALL THROUGH */ + fallthrough; case 14: reg_bitmap |= 1 << (X_Sn + 9) ; - /* FALL THROUGH */ + fallthrough; case 13: reg_bitmap |= 1 << (X_Sn + 8) ; - /* FALL THROUGH */ + fallthrough; case 12: reg_bitmap |= 1 << (X_Sn + 7) ; - /* FALL THROUGH */ + fallthrough; case 11: reg_bitmap |= 1 << (X_Sn + 6) ; - /* FALL THROUGH */ + fallthrough; case 10: reg_bitmap |= 1 << (X_Sn + 5) ; - /* FALL THROUGH */ + fallthrough; case 9: reg_bitmap |= 1 << (X_Sn + 4) ; - /* FALL THROUGH */ + fallthrough; case 8: reg_bitmap |= 1 << (X_Sn + 3) ; - /* FALL THROUGH */ + fallthrough; case 7: reg_bitmap |= 1 << (X_Sn + 2) ; - /* FALL THROUGH */ + fallthrough; case 6: reg_bitmap |= 1 << X_S1 ; - /* FALL THROUGH */ + fallthrough; case 5: reg_bitmap |= 1 << X_S0; - /* FALL THROUGH */ + fallthrough; case 4: reg_bitmap |= 1 << xRA; break; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb16..c99e513221 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -446,7 +446,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) return t; } #else - /* fall through */ + fallthrough; case MXL_RV64: return cpu_gpr[reg_num]; #endif @@ -516,7 +516,7 @@ static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); break; #else - /* fall through */ + fallthrough; case MXL_RV64: tcg_gen_mov_i64(cpu_gpr[reg_num], t); break;