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X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(13018025)(8121501046)(5005006)(13023025)(13024025)(13017025)(13015025)(10201501046)(3002001)(6055026); SRVR:BL2NAM02HT088; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT088; X-Forefront-PRVS: 0994F5E0C5 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2016 20:30:57.1979 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT088 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.37.76 Subject: [Qemu-devel] [PATCH v1 3/4] xlnx-zynqmp-ipi: Add the IPI device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the Xilinx ZynqMP Inter Processor Interrupt device. Signed-off-by: Alistair Francis --- hw/intc/Makefile.objs | 1 + hw/intc/xlnx-zynqmp-ipi.c | 263 ++++++++++++++++++++++++++++++++++++++ include/hw/intc/xlnx-zynqmp-ipi.h | 116 +++++++++++++++++ 3 files changed, 380 insertions(+) create mode 100644 hw/intc/xlnx-zynqmp-ipi.c create mode 100644 include/hw/intc/xlnx-zynqmp-ipi.h diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 530df2e..2f63bd7 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -37,3 +37,4 @@ obj-$(CONFIG_S390_FLIC) += s390_flic.o obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o diff --git a/hw/intc/xlnx-zynqmp-ipi.c b/hw/intc/xlnx-zynqmp-ipi.c new file mode 100644 index 0000000..f5f9c97 --- /dev/null +++ b/hw/intc/xlnx-zynqmp-ipi.c @@ -0,0 +1,263 @@ +/* + * QEMU model of the Xilinx ZynqMP Inter Processor Interrupt block + * + * Copyright (c) 2016 Xilinx Inc. + * Written by Edgar E. Iglesias + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "hw/intc/xlnx-zynqmp-ipi.h" + +#ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG +#define XLNX_ZYNQMP_IPI_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do {\ + if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\ + qemu_log(TYPE_XLNX_ZYNQMP_IPI ": %s:" fmt, __func__, ## args);\ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s) +{ + bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR]; + + DB_PRINT("%s: irq=%d isr=%x mask=%x\n", + object_get_canonical_path(OBJECT(s)), + pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]); + + qemu_set_irq(s->irq, pending); +} + +static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); + + xlnx_zynqmp_ipi_update_irq(s); +} + +static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); + uint32_t val = val64; + + s->regs[R_IPI_IMR] &= ~val; + xlnx_zynqmp_ipi_update_irq(s); + + return 0; +} + +static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); + uint32_t val = val64; + + s->regs[R_IPI_IMR] |= val; + xlnx_zynqmp_ipi_update_irq(s); + + return 0; +} + +static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); + uint64_t old_value = s->regs[R_IPI_TRIG]; + + /* TRIG generates a pulse on the outbound signals. We use the + * post-write callback to bring the signal back-down. + */ + s->regs[R_IPI_TRIG] = 0; + register_refresh_gpios(reg, old_value, XLNX_ZYNQMP_IPI_ERR_DEBUG); +} + +static RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = { + { .name = "IPI_TRIG", .addr = A_IPI_TRIG, + .rsvd = 0xf0f0fcfe, .ro = 0xf0f0fcfe, + .post_write = xlnx_zynqmp_ipi_trig_postw, + .gpios = (RegisterGPIOMapping[]) { + { .name = "APU", .bit_pos = R_IPI_TRIG_APU_SHIFT, .width = 1 }, + { .name = "RPU_0", .bit_pos = R_IPI_TRIG_RPU_0_SHIFT, .width = 1 }, + { .name = "RPU_1", .bit_pos = R_IPI_TRIG_RPU_1_SHIFT, .width = 1 }, + { .name = "PMU_0", .bit_pos = R_IPI_TRIG_PMU_0_SHIFT, .width = 1 }, + { .name = "PMU_1", .bit_pos = R_IPI_TRIG_PMU_1_SHIFT, .width = 1 }, + { .name = "PMU_2", .bit_pos = R_IPI_TRIG_PMU_2_SHIFT, .width = 1 }, + { .name = "PMU_3", .bit_pos = R_IPI_TRIG_PMU_3_SHIFT, .width = 1 }, + { .name = "PL_0", .bit_pos = R_IPI_TRIG_PL_0_SHIFT, .width = 1 }, + { .name = "PL_1", .bit_pos = R_IPI_TRIG_PL_1_SHIFT, .width = 1 }, + { .name = "PL_2", .bit_pos = R_IPI_TRIG_PL_2_SHIFT, .width = 1 }, + { .name = "PL_3", .bit_pos = R_IPI_TRIG_PL_3_SHIFT, .width = 1 }, + { }, + } + },{ .name = "IPI_OBS", .addr = A_IPI_OBS, + .rsvd = 0xf0f0fcfe, .ro = 0xffffffff, + },{ .name = "IPI_ISR", .addr = A_IPI_ISR, + .rsvd = 0xf0f0fcfe, .ro = 0xf0f0fcfe, .w1c = 0xf0f0301, + .post_write = xlnx_zynqmp_ipi_isr_postw, + .gpios = (RegisterGPIOMapping[]) { + { .name = "OBS_APU", .bit_pos = R_IPI_ISR_APU_SHIFT, .width = 1 }, + { .name = "OBS_RPU_0", .bit_pos = R_IPI_ISR_RPU_0_SHIFT, + .width = 1 }, + { .name = "OBS_RPU_1", .bit_pos = R_IPI_ISR_RPU_1_SHIFT, + .width = 1 }, + { .name = "OBS_PMU_0", .bit_pos = R_IPI_ISR_PMU_0_SHIFT, + .width = 1 }, + { .name = "OBS_PMU_1", .bit_pos = R_IPI_ISR_PMU_1_SHIFT, + .width = 1 }, + { .name = "OBS_PMU_2", .bit_pos = R_IPI_ISR_PMU_2_SHIFT, + .width = 1 }, + { .name = "OBS_PMU_3", .bit_pos = R_IPI_ISR_PMU_3_SHIFT, + .width = 1 }, + { .name = "OBS_PL_0", .bit_pos = R_IPI_ISR_PL_0_SHIFT, + .width = 1 }, + { .name = "OBS_PL_1", .bit_pos = R_IPI_ISR_PL_1_SHIFT, + .width = 1 }, + { .name = "OBS_PL_2", .bit_pos = R_IPI_ISR_PL_2_SHIFT, + .width = 1 }, + { .name = "OBS_PL_3", .bit_pos = R_IPI_ISR_PL_3_SHIFT, + .width = 1 }, + { }, + } + },{ .name = "IPI_IMR", .addr = A_IPI_IMR, + .reset = 0xf0f0301, .rsvd = 0xf0f0fcfe, + .ro = 0xffffffff, + },{ .name = "IPI_IER", .addr = A_IPI_IER, + .rsvd = 0xf0f0fcfe, .ro = 0xf0f0fcfe, + .pre_write = xlnx_zynqmp_ipi_ier_prew, + },{ .name = "IPI_IDR", .addr = A_IPI_IDR, + .rsvd = 0xf0f0fcfe, .ro = 0xf0f0fcfe, + .pre_write = xlnx_zynqmp_ipi_idr_prew, + } +}; + +static void xlnx_zynqmp_ipi_reset(DeviceState *dev) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } + + xlnx_zynqmp_ipi_update_irq(s); +} + +static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque); + RegisterInfo *r_isr = &s->regs_info[A_IPI_ISR / 4]; + + uint32_t val = (!!level) << n; + uint64_t old_value = s->regs[R_IPI_ISR]; + + DB_PRINT("%s: %s: irq[%d]=%d\n", __func__, + object_get_canonical_path(OBJECT(s)), n, level); + + s->regs[R_IPI_ISR] |= val; + + xlnx_zynqmp_ipi_update_irq(s); + register_refresh_gpios(r_isr, old_value, XLNX_ZYNQMP_IPI_ERR_DEBUG); +} + +static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque); + + s->regs[R_IPI_OBS] &= ~(1ULL << n); + s->regs[R_IPI_OBS] |= (level << n); +} + +static const MemoryRegionOps xlnx_zynqmp_ipi_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp) +{ + qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32); + qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32); +} + +static void xlnx_zynqmp_ipi_init(Object *obj) +{ + XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init_io(&s->iomem, obj, &xlnx_zynqmp_ipi_ops, s, + TYPE_XLNX_ZYNQMP_IPI, R_MAX * 4); + reg_array = + register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info, + ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info), + s->regs_info, s->regs, + &xlnx_zynqmp_ipi_ops, XLNX_ZYNQMP_IPI_ERR_DEBUG, + R_MAX); + memory_region_add_subregion(&s->iomem, + A_IPI_IDR, + ®_array->mem); + + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static const VMStateDescription vmstate_ipi = { + .name = TYPE_XLNX_ZYNQMP_IPI, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = xlnx_zynqmp_ipi_reset; + dc->realize = xlnx_zynqmp_ipi_realize; + dc->vmsd = &vmstate_ipi; +} + +static const TypeInfo xlnx_zynqmp_ipi_info = { + .name = TYPE_XLNX_ZYNQMP_IPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxZynqMPIPI), + .class_init = xlnx_zynqmp_ipi_class_init, + .instance_init = xlnx_zynqmp_ipi_init, +}; + +static void xlnx_zynqmp_ipi_register_types(void) +{ + type_register_static(&xlnx_zynqmp_ipi_info); +} + +type_init(xlnx_zynqmp_ipi_register_types) diff --git a/include/hw/intc/xlnx-zynqmp-ipi.h b/include/hw/intc/xlnx-zynqmp-ipi.h new file mode 100644 index 0000000..065d130 --- /dev/null +++ b/include/hw/intc/xlnx-zynqmp-ipi.h @@ -0,0 +1,116 @@ +/* + * QEMU model of the Xilinx ZynqMP Inter Processor Interrupt block + * + * Copyright (c) 2016 Xilinx Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/register.h" + +#define TYPE_XLNX_ZYNQMP_IPI "xlnx.zynqmp.ipi" + +#define XLNX_ZYNQMP_IPI(obj) \ + OBJECT_CHECK(XlnxZynqMPIPI, (obj), TYPE_XLNX_ZYNQMP_IPI) + +REG32(IPI_TRIG, 0x0) + FIELD(IPI_TRIG, PL_3, 27, 1) + FIELD(IPI_TRIG, PL_2, 26, 1) + FIELD(IPI_TRIG, PL_1, 25, 1) + FIELD(IPI_TRIG, PL_0, 24, 1) + FIELD(IPI_TRIG, PMU_3, 19, 1) + FIELD(IPI_TRIG, PMU_2, 18, 1) + FIELD(IPI_TRIG, PMU_1, 17, 1) + FIELD(IPI_TRIG, PMU_0, 16, 1) + FIELD(IPI_TRIG, RPU_1, 9, 1) + FIELD(IPI_TRIG, RPU_0, 8, 1) + FIELD(IPI_TRIG, APU, 0, 1) +REG32(IPI_OBS, 0x4) + FIELD(IPI_OBS, PL_3, 27, 1) + FIELD(IPI_OBS, PL_2, 26, 1) + FIELD(IPI_OBS, PL_1, 25, 1) + FIELD(IPI_OBS, PL_0, 24, 1) + FIELD(IPI_OBS, PMU_3, 19, 1) + FIELD(IPI_OBS, PMU_2, 18, 1) + FIELD(IPI_OBS, PMU_1, 17, 1) + FIELD(IPI_OBS, PMU_0, 16, 1) + FIELD(IPI_OBS, RPU_1, 9, 1) + FIELD(IPI_OBS, RPU_0, 8, 1) + FIELD(IPI_OBS, APU, 0, 1) +REG32(IPI_ISR, 0x10) + FIELD(IPI_ISR, PL_3, 27, 1) + FIELD(IPI_ISR, PL_2, 26, 1) + FIELD(IPI_ISR, PL_1, 25, 1) + FIELD(IPI_ISR, PL_0, 24, 1) + FIELD(IPI_ISR, PMU_3, 19, 1) + FIELD(IPI_ISR, PMU_2, 18, 1) + FIELD(IPI_ISR, PMU_1, 17, 1) + FIELD(IPI_ISR, PMU_0, 16, 1) + FIELD(IPI_ISR, RPU_1, 9, 1) + FIELD(IPI_ISR, RPU_0, 8, 1) + FIELD(IPI_ISR, APU, 0, 1) +REG32(IPI_IMR, 0x14) + FIELD(IPI_IMR, PL_3, 27, 1) + FIELD(IPI_IMR, PL_2, 26, 1) + FIELD(IPI_IMR, PL_1, 25, 1) + FIELD(IPI_IMR, PL_0, 24, 1) + FIELD(IPI_IMR, PMU_3, 19, 1) + FIELD(IPI_IMR, PMU_2, 18, 1) + FIELD(IPI_IMR, PMU_1, 17, 1) + FIELD(IPI_IMR, PMU_0, 16, 1) + FIELD(IPI_IMR, RPU_1, 9, 1) + FIELD(IPI_IMR, RPU_0, 8, 1) + FIELD(IPI_IMR, APU, 0, 1) +REG32(IPI_IER, 0x18) + FIELD(IPI_IER, PL_3, 27, 1) + FIELD(IPI_IER, PL_2, 26, 1) + FIELD(IPI_IER, PL_1, 25, 1) + FIELD(IPI_IER, PL_0, 24, 1) + FIELD(IPI_IER, PMU_3, 19, 1) + FIELD(IPI_IER, PMU_2, 18, 1) + FIELD(IPI_IER, PMU_1, 17, 1) + FIELD(IPI_IER, PMU_0, 16, 1) + FIELD(IPI_IER, RPU_1, 9, 1) + FIELD(IPI_IER, RPU_0, 8, 1) + FIELD(IPI_IER, APU, 0, 1) +REG32(IPI_IDR, 0x1c) + FIELD(IPI_IDR, PL_3, 27, 1) + FIELD(IPI_IDR, PL_2, 26, 1) + FIELD(IPI_IDR, PL_1, 25, 1) + FIELD(IPI_IDR, PL_0, 24, 1) + FIELD(IPI_IDR, PMU_3, 19, 1) + FIELD(IPI_IDR, PMU_2, 18, 1) + FIELD(IPI_IDR, PMU_1, 17, 1) + FIELD(IPI_IDR, PMU_0, 16, 1) + FIELD(IPI_IDR, RPU_1, 9, 1) + FIELD(IPI_IDR, RPU_0, 8, 1) + FIELD(IPI_IDR, APU, 0, 1) + +#define R_MAX (R_IPI_IDR + 1) + +typedef struct XlnxZynqMPIPI { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[R_MAX]; + RegisterInfo regs_info[R_MAX]; +} XlnxZynqMPIPI;