From patchwork Wed Dec 26 08:25:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 10742915 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 656B8924 for ; Wed, 26 Dec 2018 08:22:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54F38288DB for ; Wed, 26 Dec 2018 08:22:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4803228957; Wed, 26 Dec 2018 08:22:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D4180288DB for ; Wed, 26 Dec 2018 08:22:32 +0000 (UTC) Received: from localhost ([127.0.0.1]:44852 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gc4SW-0006wo-1f for patchwork-qemu-devel@patchwork.kernel.org; Wed, 26 Dec 2018 03:22:32 -0500 Received: from eggs.gnu.org ([208.118.235.92]:50657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gc4RH-0005iN-6N for qemu-devel@nongnu.org; Wed, 26 Dec 2018 03:21:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gc4RD-0005pW-7e for qemu-devel@nongnu.org; Wed, 26 Dec 2018 03:21:15 -0500 Received: from mga06.intel.com ([134.134.136.31]:14740) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gc4RB-0005oB-82 for qemu-devel@nongnu.org; Wed, 26 Dec 2018 03:21:11 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Dec 2018 00:21:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,400,1539673200"; d="scan'208";a="103379568" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.239.13.104]) by orsmga006.jf.intel.com with ESMTP; 26 Dec 2018 00:21:05 -0800 From: Yang Weijiang To: qemu-devel@nongnu.org, pbonzini@redhat.com, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, mst@redhat.com, yu-cheng.yu@intel.com, yi.z.zhang@intel.com, hjl.tools@gmail.com Date: Wed, 26 Dec 2018 16:25:17 +0800 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.31 Subject: [Qemu-devel] [PATCH 1/4] Add CET xsaves/xrstors related macros and structures. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang , Zhang Yi Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP CET protection in user mode and kernel mode relies on specific MSRs, these MSRs' contents are automatically saved/restored by xsaves/xrstors instructions. Signed-off-by: Zhang Yi Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9c52d0cbeb..f3f724d8e6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -469,6 +469,9 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_RESERVED_BIT 10 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -479,6 +482,19 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_RESERVED_MASK (1ULL << XSTATE_RESERVED_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) + +/* CPUID feature bits available in XCR0 */ +#define CPUID_XSTATE_USER_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK \ + | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK \ + | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK \ + | XSTATE_ZMM_Hi256_MASK \ + | XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) + +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_KERNEL_MASK (XSTATE_CET_U_MASK | XSTATE_CET_S_MASK) /* CPUID feature words */ typedef enum FeatureWord { @@ -503,6 +519,8 @@ typedef enum FeatureWord { FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ FEAT_ARCH_CAPABILITIES, + FEAT_XSAVE_SV_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ + FEAT_XSAVE_SV_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEATURE_WORDS, } FeatureWord; @@ -687,7 +705,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_LA57 (1U << 16) #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ - +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* CET SHSTK feature bit */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_PCONFIG (1U << 18) /* Platform Configuration */ @@ -1021,6 +1039,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; +/* Ext. save area 11: User mode CET state */ +typedef struct XSaveCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSaveCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSaveCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSaveCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; @@ -1039,6 +1070,9 @@ typedef struct X86XSaveArea { XSaveHi16_ZMM hi16_zmm_state; /* PKRU State: */ XSavePKRU pkru_state; + /* CET State: */ + XSaveCETU cet_u; + XSaveCETS cet_s; } X86XSaveArea; QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);