Message ID | c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | ppc4xx_sdram QOMify and clean ups | expand |
On 9/24/22 09:28, BALATON Zoltan wrote: > Remove the do_init parameter of ppc440_sdram_init and enable SDRAM > controller from the board. Firmware does this so it may only be needed > when booting with -kernel without firmware but we enable SDRAM > unconditionally to preserve previous behaviour. > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > v5: Add function to enable sdram controller > > hw/ppc/ppc440.h | 3 +-- > hw/ppc/ppc440_uc.c | 15 +++++++++------ > hw/ppc/sam460ex.c | 4 +++- > include/hw/ppc/ppc4xx.h | 2 ++ > 4 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h > index e6c905b7d6..01d76b8000 100644 > --- a/hw/ppc/ppc440.h > +++ b/hw/ppc/ppc440.h > @@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env); > void ppc4xx_cpr_init(CPUPPCState *env); > void ppc4xx_sdr_init(CPUPPCState *env); > void ppc440_sdram_init(CPUPPCState *env, int nbanks, > - Ppc4xxSdramBank *ram_banks, > - int do_init); > + Ppc4xxSdramBank *ram_banks); > void ppc4xx_ahb_init(CPUPPCState *env); > void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); > void ppc460ex_pcie_init(CPUPPCState *env); > diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c > index 3fbfe4ad13..e8bc088c8f 100644 > --- a/hw/ppc/ppc440_uc.c > +++ b/hw/ppc/ppc440_uc.c > @@ -16,6 +16,7 @@ > #include "qemu/module.h" > #include "hw/irq.h" > #include "exec/memory.h" > +#include "cpu.h" > #include "hw/ppc/ppc4xx.h" > #include "hw/qdev-properties.h" > #include "hw/pci/pci.h" > @@ -727,12 +728,11 @@ static void sdram_reset(void *opaque) > ppc440_sdram_t *sdram = opaque; > > sdram->addr = 0; > - sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN; > + sdram->mcopt2 = 0; > } > > void ppc440_sdram_init(CPUPPCState *env, int nbanks, > - Ppc4xxSdramBank *ram_banks, > - int do_init) > + Ppc4xxSdramBank *ram_banks) > { > ppc440_sdram_t *sdram; > int i; > @@ -749,9 +749,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, > sdram, &dcr_read_sdram, &dcr_write_sdram); > ppc_dcr_register(env, SDRAM0_CFGDATA, > sdram, &dcr_read_sdram, &dcr_write_sdram); > - if (do_init) { > - sdram_map_bcr(sdram); > - } > > ppc_dcr_register(env, SDRAM_R0BAS, > sdram, &dcr_read_sdram, &dcr_write_sdram); > @@ -773,6 +770,12 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, > sdram, &dcr_read_sdram, &dcr_write_sdram); > } > > +void ppc440_sdram_enable(CPUPPCState *env) > +{ > + ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21); > + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000); > +} > + > /*****************************************************************************/ > /* PLB to AHB bridge */ > enum { > diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c > index f4c2a693fb..9c01211b20 100644 > --- a/hw/ppc/sam460ex.c > +++ b/hw/ppc/sam460ex.c > @@ -345,7 +345,9 @@ static void sam460ex_init(MachineState *machine) > ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes); > > /* FIXME: does 460EX have ECC interrupts? */ > - ppc440_sdram_init(env, 1, ram_banks, 1); > + ppc440_sdram_init(env, 1, ram_banks); > + /* Enable SDRAM memory regions as we may boot without firmware */ > + ppc440_sdram_enable(env); > > /* IIC controllers and devices */ > dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, > diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h > index 558500fb97..78a845399e 100644 > --- a/include/hw/ppc/ppc4xx.h > +++ b/include/hw/ppc/ppc4xx.h > @@ -37,6 +37,8 @@ typedef struct { > uint32_t bcr; > } Ppc4xxSdramBank; > > +void ppc440_sdram_enable(CPUPPCState *env); > + > void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, > Ppc4xxSdramBank ram_banks[], > const ram_addr_t sdram_bank_sizes[]);
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index e6c905b7d6..01d76b8000 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init); + Ppc4xxSdramBank *ram_banks); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); void ppc460ex_pcie_init(CPUPPCState *env); diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 3fbfe4ad13..e8bc088c8f 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -16,6 +16,7 @@ #include "qemu/module.h" #include "hw/irq.h" #include "exec/memory.h" +#include "cpu.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" #include "hw/pci/pci.h" @@ -727,12 +728,11 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram = opaque; sdram->addr = 0; - sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN; + sdram->mcopt2 = 0; } void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init) + Ppc4xxSdramBank *ram_banks) { ppc440_sdram_t *sdram; int i; @@ -749,9 +749,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) { - sdram_map_bcr(sdram); - } ppc_dcr_register(env, SDRAM_R0BAS, sdram, &dcr_read_sdram, &dcr_write_sdram); @@ -773,6 +770,12 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); } +void ppc440_sdram_enable(CPUPPCState *env) +{ + ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21); + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000); +} + /*****************************************************************************/ /* PLB to AHB bridge */ enum { diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index f4c2a693fb..9c01211b20 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -345,7 +345,9 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes); /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, 1, ram_banks, 1); + ppc440_sdram_init(env, 1, ram_banks); + /* Enable SDRAM memory regions as we may boot without firmware */ + ppc440_sdram_enable(env); /* IIC controllers and devices */ dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 558500fb97..78a845399e 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -37,6 +37,8 @@ typedef struct { uint32_t bcr; } Ppc4xxSdramBank; +void ppc440_sdram_enable(CPUPPCState *env); + void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, Ppc4xxSdramBank ram_banks[], const ram_addr_t sdram_bank_sizes[]);
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM controller from the board. Firmware does this so it may only be needed when booting with -kernel without firmware but we enable SDRAM unconditionally to preserve previous behaviour. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- v5: Add function to enable sdram controller hw/ppc/ppc440.h | 3 +-- hw/ppc/ppc440_uc.c | 15 +++++++++------ hw/ppc/sam460ex.c | 4 +++- include/hw/ppc/ppc4xx.h | 2 ++ 4 files changed, 15 insertions(+), 9 deletions(-)