From patchwork Thu Apr 20 20:43:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 9691315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 95A43601D4 for ; Thu, 20 Apr 2017 21:02:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 82CBC26B41 for ; Thu, 20 Apr 2017 21:02:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7470726E4D; Thu, 20 Apr 2017 21:02:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0B09526B41 for ; Thu, 20 Apr 2017 21:02:11 +0000 (UTC) Received: from localhost ([::1]:55981 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d1JDO-0001JB-9u for patchwork-qemu-devel@patchwork.kernel.org; Thu, 20 Apr 2017 17:02:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51652) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d1J82-0005et-7U for qemu-devel@nongnu.org; Thu, 20 Apr 2017 16:56:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d1J80-00052s-2X for qemu-devel@nongnu.org; Thu, 20 Apr 2017 16:56:38 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:30675) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d1J7z-00051Y-Rj; Thu, 20 Apr 2017 16:56:36 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 27C6F7456FD; Thu, 20 Apr 2017 22:56:24 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id C071B7456B9; Thu, 20 Apr 2017 22:56:16 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Thu, 20 Apr 2017 22:43:46 +0200 To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v5 03/13] sm501: Add missing arbitration control register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Magnus Damm , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: BALATON Zoltan Reviewed-by: Peter Maydell --- hw/display/sm501.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 6b72964..6e74200 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -474,6 +474,7 @@ typedef struct SM501State { uint32_t gpio_31_0_control; uint32_t gpio_63_32_control; uint32_t dram_control; + uint32_t arbitration_control; uint32_t irq_mask; uint32_t misc_timing; uint32_t power_mode_control; @@ -757,6 +758,9 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr, case SM501_DRAM_CONTROL: ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; break; + case SM501_ARBTRTN_CONTROL: + ret = s->arbitration_control; + break; case SM501_IRQ_MASK: ret = s->irq_mask; break; @@ -809,6 +813,9 @@ static void sm501_system_config_write(void *opaque, hwaddr addr, /* TODO : check validity of size change */ s->dram_control |= value & 0x7FFFFFC3; break; + case SM501_ARBTRTN_CONTROL: + s->arbitration_control = value & 0x37777777; + break; case SM501_IRQ_MASK: s->irq_mask = value; break; @@ -1422,6 +1429,7 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base, * BUS = 0 : Hitachi SH3/SH4 */ s->misc_control = SM501_MISC_DAC_POWER; + s->arbitration_control = 0x05146732; s->dc_panel_control = 0x00010000; /* FIFO level 3 */ s->dc_crt_control = 0x00010000;