From patchwork Fri Nov 4 20:50:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 9413337 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D65F96022E for ; Fri, 4 Nov 2016 21:18:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C69212AC90 for ; Fri, 4 Nov 2016 21:18:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BAD972B0FF; Fri, 4 Nov 2016 21:18:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 46B7B2AC90 for ; Fri, 4 Nov 2016 21:18:08 +0000 (UTC) Received: from localhost ([::1]:40839 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2lsF-0006X8-Cm for patchwork-qemu-devel@patchwork.kernel.org; Fri, 04 Nov 2016 17:18:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2lSn-00019z-A7 for qemu-devel@nongnu.org; Fri, 04 Nov 2016 16:51:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2lSm-0004NZ-0X for qemu-devel@nongnu.org; Fri, 04 Nov 2016 16:51:49 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:34147) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c2lSl-0004MQ-OS for qemu-devel@nongnu.org; Fri, 04 Nov 2016 16:51:47 -0400 Received: by mail-wm0-x241.google.com with SMTP id p190so5635983wmp.1 for ; Fri, 04 Nov 2016 13:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=1t1Jy8rses5uVX21S2rsq1+FyVnx6EyAMHK6/7qW3OE=; b=UzLC8XFJYPbYDVpiM9zq+etUi7iMiixKmVLcYeHWLQjKoXeqsYuE77JoxkTm0myXIK +BQY+5u/YReyuk/jsYqj27jn9G9erCk42rcyfjktQde+g6D3TxDIKN3JTZ9W6O/wyAyF o/FAA4E6e20NWEXFNvDoCb7QYUe1cLAzmP3XEfJP0S00SypAAKo4qZwA3Ta6j3uIzKNI aFw8U6/JfSWqGWOzec0zJWN2utsviRUfmNb/HvyNG0HRxKGSq+ls14SRlf/FiQSL/HWe 5z6/WiCqy/iE62hVbbDyYSbWGuqMc5V/eA78C/KppM9UwTRM4bDUuukxOssRtGidPBar ryDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1t1Jy8rses5uVX21S2rsq1+FyVnx6EyAMHK6/7qW3OE=; b=GB/osIGuyS7VP4JVUAzgDLmnaz1L8iEhgiXjGImU7r/f+deNncqwZrB6pHhsGEa27K /sNb0x3JH09aZJjuWnyA50nAld0WmktAqmtQ0xtapjmlKrs6+nFhsqzc3rg7qVzNAV/A 5qQn7K7I8hrLUwTbzBaMGJ22FS3VStwaQnTvIft9LiSNWZtN6Q82CVjibL+20MYn8vHy zUBHear/+uR+v79QFYeDXItskZhe6SpOJgqGzsjI0BvTOsSeRFsmRHbFmIvLf5ZFVm0D 8rZbMmJ50p7Zp7wCiPVIqw4p/Pw/oIheAw0MTqzV6jNTJ5amuzU7W55o5yPhnGwjMByT p5qg== X-Gm-Message-State: ABUngvcVPJne8h8DCl+kFl8BW6Wvr0BbyLeuW86xauw4OfrBunYwrxXSHyQbj0TlSNAwUQ== X-Received: by 10.194.238.162 with SMTP id vl2mr13173661wjc.39.1478292706195; Fri, 04 Nov 2016 13:51:46 -0700 (PDT) Received: from localhost (x55b4b5cf.dyn.telefonica.de. [85.180.181.207]) by smtp.gmail.com with ESMTPSA id v2sm16121794wja.41.2016.11.04.13.51.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Nov 2016 13:51:44 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Fri, 4 Nov 2016 21:50:22 +0100 Message-Id: X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v1 21/30] target-sparc: simplify ultrasparc_tsb_pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Artyom Tarasenko --- target-sparc/ldst_helper.c | 51 ++++++++++++++-------------------------------- 1 file changed, 15 insertions(+), 36 deletions(-) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 4b8ca69..0447d4e 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -70,44 +70,35 @@ #define QT1 (env->qt1) #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) -static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, uint64_t tsb, - uint64_t *tsb_ptr, - uint64_t tag_access_register, - int idx, uint64_t *cfg_ptr) /* Calculates TSB pointer value for fault page size * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers * UA2005 holds the page size configuration in mmu_ctx registers */ +static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, + const SparcV9MMU *mmu, const int idx) { uint64_t tsb_register; int page_size; if (cpu_has_hypervisor(env)) { int tsb_index = 0; - int ctx = tag_access_register & 0x1fffULL; - uint64_t ctx_register = cfg_ptr[ctx ? 1 : 0]; + int ctx = mmu->tag_access & 0x1fffULL; + uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; tsb_index = idx; tsb_index |= ctx ? 2 : 0; page_size = idx ? ctx_register >> 8 : ctx_register; page_size &= 7; - tsb_register = tsb_ptr[tsb_index]; + tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; } else { page_size = idx; - tsb_register = tsb; + tsb_register = mmu->tsb; } - uint64_t tsb_base = tsb_register & ~0x1fffULL; int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; int tsb_size = tsb_register & 0xf; - /* discard lower 13 bits which hold tag access context */ - uint64_t tag_access_va = tag_access_register & ~0x1fffULL; + uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size; - /* now reorder bits */ - uint64_t tsb_base_mask = ~0x1fffULL; - uint64_t va = tag_access_va; - - /* move va bits to correct position */ - va >>= 3 * page_size + 9; - - tsb_base_mask <<= tsb_size; + /* move va bits to correct position, + * the context bits will be masked out later */ + uint64_t va = mmu->tag_access >> (3 * page_size + 9); /* calculate tsb_base mask and adjust va if split is in use */ if (tsb_split) { @@ -119,7 +110,7 @@ static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env, uint64_t tsb, tsb_base_mask <<= 1; } - return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; + return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; } /* Calculates tag target register value by reordering bits @@ -1266,20 +1257,14 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, { /* env->immuregs[5] holds I-MMU TSB register value env->immuregs[6] holds I-MMU Tag Access register value */ - ret = ultrasparc_tsb_pointer(env, env->immu.tsb, - env->immu.sun4v_tsb_pointers, - env->immu.tag_access, - 0, env->immu.sun4v_ctx_config); + ret = ultrasparc_tsb_pointer(env, &env->immu, 0); break; } case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ { /* env->immuregs[5] holds I-MMU TSB register value env->immuregs[6] holds I-MMU Tag Access register value */ - ret = ultrasparc_tsb_pointer(env, env->immu.tsb, - env->immu.sun4v_tsb_pointers, - env->immu.tag_access, - 1, env->immu.sun4v_ctx_config); + ret = ultrasparc_tsb_pointer(env, &env->immu, 1); break; } case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ @@ -1338,20 +1323,14 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, { /* env->dmmuregs[5] holds D-MMU TSB register value env->dmmuregs[6] holds D-MMU Tag Access register value */ - ret = ultrasparc_tsb_pointer(env, env->dmmu.tsb, - env->dmmu.sun4v_tsb_pointers, - env->dmmu.tag_access, - 0, env->dmmu.sun4v_ctx_config); + ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); break; } case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ { /* env->dmmuregs[5] holds D-MMU TSB register value env->dmmuregs[6] holds D-MMU Tag Access register value */ - ret = ultrasparc_tsb_pointer(env, env->dmmu.tsb, - env->dmmu.sun4v_tsb_pointers, - env->dmmu.tag_access, - 1, env->dmmu.sun4v_ctx_config); + ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); break; } case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */