diff mbox series

[RFC,v1,20/23] riscv: tcg-target: Add the target init code

Message ID cd89e90aeb79ed438aaee6cfa02ca42a36d633b6.1542321076.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V TCG backend support | expand

Commit Message

Alistair Francis Nov. 15, 2018, 10:36 p.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 tcg/riscv/tcg-target.inc.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

Comments

Richard Henderson Nov. 16, 2018, 5:26 p.m. UTC | #1 
On 11/15/18 11:36 PM, Alistair Francis wrote:
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);

Why are these three reserved?


r~
Alistair Francis Nov. 19, 2018, 11:04 p.m. UTC | #2 
On Fri, Nov 16, 2018 at 9:26 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/15/18 11:36 PM, Alistair Francis wrote:
> > +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
> > +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
> > +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
>
> Why are these three reserved?

Do these not need to be? I thought we had to reserve them.

Alistair

>
>
> r~
Richard Henderson Nov. 20, 2018, 6:55 a.m. UTC | #3 
On 11/20/18 12:04 AM, Alistair Francis wrote:
> On Fri, Nov 16, 2018 at 9:26 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 11/15/18 11:36 PM, Alistair Francis wrote:
>>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
>>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
>>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
>>
>> Why are these three reserved?
> 
> Do these not need to be? I thought we had to reserve them.

The return address, I presume, has been saved by the prologue.  I see no reason
why it can't be yet another call-clobbered register.

As for the other two... what are they supposed to be?


r~
Alistair Francis Nov. 20, 2018, 11:22 p.m. UTC | #4 
On Mon, Nov 19, 2018 at 10:55 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/20/18 12:04 AM, Alistair Francis wrote:
> > On Fri, Nov 16, 2018 at 9:26 AM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 11/15/18 11:36 PM, Alistair Francis wrote:
> >>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
> >>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
> >>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
> >>
> >> Why are these three reserved?
> >
> > Do these not need to be? I thought we had to reserve them.
>
> The return address, I presume, has been saved by the prologue.  I see no reason
> why it can't be yet another call-clobbered register.

Ok, removed.

>
> As for the other two... what are they supposed to be?

They were old temp registers. L1 wasn't even used and I have replace
L0 with TMP0 as we have enough tmp registers.

Alistair

>
>
> r~
diff mbox series

Patch

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 4b8f65f367..dfc4e8b44c 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1641,6 +1641,39 @@  static void tcg_target_qemu_prologue(TCGContext *s)
     tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
 }
 
+static void tcg_target_init(TCGContext *s)
+{
+    tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
+    if (TCG_TARGET_REG_BITS == 64) {
+        tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
+    }
+
+    tcg_target_call_clobber_regs = -1u;
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
+    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
+
+    s->reserved_regs = 0;
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
+    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
                               uintptr_t addr)
 {