@@ -147,7 +147,17 @@ static void sifive_plic_update(SiFivePLICState *plic)
riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
break;
case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
+ if (riscv_cpu_virt_enabled(env)) {
+ if (level) {
+ atomic_or(&env->bsip, MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ } else {
+ atomic_and(&env->bsip, ~MIP_SEIP);
+ g_assert(riscv_cpu_virt_enabled(env));
+ }
+ } else {
+ riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
+ }
break;
default:
break;
When the PLIC generates an interrupt ensure we always set it for the SIP CSR that corresponds to the HS (V=0) register. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_plic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)