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Wed, 17 Mar 2021 02:28:46 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id r30sm18630163pgu.86.2021.03.17.02.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 02:28:46 -0700 (PDT) From: Haibo Xu To: dgilbert@redhat.com, quintela@redhat.com, drjones@redhat.com, richard.henderson@linaro.org Subject: [RFC PATCH v2 2/5] Add basic MTE support to KVM guest Date: Wed, 17 Mar 2021 09:28:21 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=haibo.xu@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Enable the virt machine feature "mte" to work with KVM guest. This feature is still hiden from the user in this patch, and will be available in a later patch. Signed-off-by: Haibo Xu --- hw/arm/virt.c | 22 +++++++++++----------- target/arm/cpu.c | 2 +- target/arm/kvm.c | 9 +++++++++ target/arm/kvm64.c | 7 +++++++ 4 files changed, 28 insertions(+), 12 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index aa2bbd14e0..76658b93a3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1988,18 +1988,18 @@ static void machvirt_init(MachineState *machine) } if (vms->mte) { + /* + * The property exists only if MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (!object_property_find(cpuobj, "tag-memory")) { + error_report("MTE requested, but not supported " + "by the guest CPU"); + exit(1); + } + /* Create the memory region only once, but link to all cpus. */ - if (!tag_sysmem) { - /* - * The property exists only if MemTag is supported. - * If it is, we must allocate the ram to back that up. - */ - if (!object_property_find(cpuobj, "tag-memory")) { - error_report("MTE requested, but not supported " - "by the guest CPU"); - exit(1); - } - + if (!tag_sysmem && !kvm_enabled()) { tag_sysmem = g_new(MemoryRegion, 1); memory_region_init(tag_sysmem, OBJECT(machine), "tag-memory", UINT64_MAX / 32); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae04884408..47bf817b61 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1847,7 +1847,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->secure_memory); } - if (cpu->tag_memory != NULL) { + if (cpu->tag_memory != NULL && !kvm_enabled()) { cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", cpu->tag_memory); if (has_secure) { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d8381ba224..3403e621ac 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -32,6 +32,7 @@ #include "hw/boards.h" #include "hw/irq.h" #include "qemu/log.h" +#include "hw/arm/virt.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO @@ -274,6 +275,14 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } + if (kvm_check_extension(s, KVM_CAP_ARM_MTE) && + object_dynamic_cast(OBJECT(ms), TYPE_VIRT_MACHINE) && + VIRT_MACHINE(ms)->mte) { + if (kvm_vm_enable_cap(s, KVM_CAP_ARM_MTE, 0)) { + error_report("Failed to enable KVM_CAP_ARM_MTE cap"); + } + } + return ret; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index dff85f6db9..73a191f8e1 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -500,6 +500,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) */ int fdarray[3]; bool sve_supported; + bool mte_supported; uint64_t features = 0; uint64_t t; int err; @@ -646,6 +647,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + mte_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_MTE) > 0; kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -659,6 +661,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); ahcf->isar.id_aa64pfr0 = t; } + if (mte_supported) { + t = ahcf->isar.id_aa64pfr1; + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); + ahcf->isar.id_aa64pfr1 = t; + } /* * We can assume any KVM supporting CPU is at least a v8