diff mbox series

[for,4.0,v1,3/5] riscv: sifive_e: Fix PLIC priority base offset

Message ID dfb27380e9c06f6e0ac59197934232993d7590d0.1553129005.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series Update the QEMU PLIC addresses | expand

Commit Message

Alistair Francis March 21, 2019, 12:46 a.m. UTC 
According to the FE31 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_e.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 7b6d8aed96..f715f8606f 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -70,7 +70,7 @@  enum {
 #define SIFIVE_E_PLIC_HART_CONFIG "M"
 #define SIFIVE_E_PLIC_NUM_SOURCES 127
 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7
-#define SIFIVE_E_PLIC_PRIORITY_BASE 0x0
+#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000
 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80