| Message ID | e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | tcg/riscv: Fix StoreStore barrier generation | expand |
On 12/11/24 01:40, Roman Artemev wrote: > On RISC-V to StoreStore barrier corresponds > `fence w, w` not `fence r, r` > > Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com> > Signed-off-by: Roman Artemev <roman.artemev@syntacore.com> > --- > tcg/riscv/tcg-target.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index f8331e4688..96f9a7e348 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1624,7 +1624,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) > insn |= 0x02100000; > } > if (a0 & TCG_MO_ST_ST) { > - insn |= 0x02200000; > + insn |= 0x01100000; > } > tcg_out32(s, insn); > } Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Wow, that typo has been around for a while. Thanks, queued. r~
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f8331e4688..96f9a7e348 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1624,7 +1624,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) insn |= 0x02100000; } if (a0 & TCG_MO_ST_ST) { - insn |= 0x02200000; + insn |= 0x01100000; } tcg_out32(s, insn); }