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[v1,5/6] target/riscv: Deprecate the generic no MMU CPUs

Message ID e327e7d2a5e0fd44b6f81c454fc830b18daa9365.1555726824.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: Add properties to the CPUs | expand

Commit Message

Alistair Francis April 20, 2019, 2:24 a.m. UTC 
These can now be specified via the command line so we no longer need
these.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 qemu-deprecated.texi | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 92ce909e50..d01fdf9907 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -137,6 +137,12 @@  four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` an
 ``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
 option when using the ``rv32`` or ``rv64`` CPUs.
 
+@subsection RISC-V ISA CPUs (since 4.1)
+
+The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
+``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
+via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
+
 @section System emulator devices
 
 @subsection bluetooth (since 3.1)