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16 Dec 2020 10:06:26 -0800 IronPort-SDR: S8WkY8LPWR25wFilwAn/1Z+gNPh7C8bt6hu5pg31jIkRDkjfaqhfc15lIs/OQbnUFGM3zeLU3L yR1vzpobd11VMSHyvq0BVjvFCUj2ejcf9c8nbK51+BO33myxD3z8Mw1EiTpLopChko5ZIjKdbL mGL2yLK3fnvIJy0KWiBqRWYyKEgnRX/wZzV5P/Vcvevu6RCSCxMEdzh2cnn5pwsx14hPfAG4ql Lx/0EG3tyfxNQdFwDXsYIU4v9Q36PkwEtx2lUnqasWsxUF8/77Ypy71gTs8Ah4oeafo9tLrnyD AD4= WDCIronportException: Internal Received: from 1996l72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.67]) by uls-op-cesaip02.wdc.com with ESMTP; 16 Dec 2020 10:22:51 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function Date: Wed, 16 Dec 2020 10:22:51 -0800 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=612374860=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9c064f3094..6339e84819 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -384,6 +384,8 @@ FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +bool riscv_cpu_is_32bit(CPURISCVState *env); + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b..32a6916b8a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,6 +108,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } +bool riscv_cpu_is_32bit(CPURISCVState *env) +{ + if (env->misa & RV64) { + return false; + } + + return true; +} + static void set_misa(CPURISCVState *env, target_ulong misa) { env->misa_mask = env->misa = misa;