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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id h2sm17599747pfk.93.2020.07.28.01.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 01:26:26 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Date: Tue, 28 Jul 2020 16:26:15 +0800 Message-Id: X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=zong.li@sifive.com; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , Zong Li Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original implementation, the second parameter of pmp_write_cfg is "reg_index * sizeof(target_ulong)", and we get the the result which is started from 16 if reg_index is 2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/pmp.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a2b9f5363..aeba796484 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -318,6 +318,10 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, return; } +#if defined(TARGET_RISCV64) + reg_index >>= 1; +#endif + for (i = 0; i < sizeof(target_ulong); i++) { cfg_val = (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i, @@ -335,11 +339,16 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) target_ulong cfg_val = 0; target_ulong val = 0; + trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); + +#if defined(TARGET_RISCV64) + reg_index >>= 1; +#endif + for (i = 0; i < sizeof(target_ulong); i++) { val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); cfg_val |= (val << (i * 8)); } - trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); return cfg_val; }