Message ID | f78aa143d508c5fd0f54da4f31c339e79ebdd105.1625704980.git.isaku.yamahata@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | TDX support | expand |
On 7/7/21 7:54 PM, isaku.yamahata@gmail.com wrote: > From: Sean Christopherson <sean.j.christopherson@intel.com> > > Expose x86_cpu_get_supported_feature_word() outside of cpu.c so that it > can be used by TDX to setup the VM-wide CPUID configuration. > > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Reviewed-by: Connor Kuehl <ckuehl@redhat.com>
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d8f3ab3192..45b81a63df 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4894,8 +4894,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) return cpu_list; } -static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, - bool migratable_only) +uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + bool migratable_only) { FeatureWordInfo *wi = &feature_word_info[w]; uint64_t r = 0; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f7fa5870b1..ff8f9532b9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1838,6 +1838,9 @@ void cpu_clear_ignne(void); /* mpx_helper.c */ void cpu_sync_bndcs_hflags(CPUX86State *env); +uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + bool migratable_only); + /* this function must always be used to load data in the segment cache: it synchronizes the hflags with the segment cache values */ static inline void cpu_x86_load_seg_cache(CPUX86State *env,