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14 Dec 2020 12:17:45 -0800 IronPort-SDR: Mp9FgjYmP8Z6/r/GVaTcFhu6ogltrSUgRFJdQlw0Usbp/44JurnM4d0BGui4+hpjCtzkhJIyUk xzmnfJl07jLnVUqDVxLdfLD63XWF8G2j87/Wi0r9m2rS6I31yMPjs2dKxyQ0i36c+/boG5YuBH n3KxgEjNE5vRsC7IdqzysukGcdFLJcHpLF5DzAJ4J+Ev6re2szxJ+6D1lXvfAzNNnxbBKYupL7 P9uP/m73h13J5qp1Mh89jXxSuxinQDyJ6dGuPap6rVq5oS2nJI7Zqb6TDSa8+YTZpqDYMSx5pO jUM= WDCIronportException: Internal Received: from cnf006900.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.52]) by uls-op-cesaip02.wdc.com with ESMTP; 14 Dec 2020 12:34:02 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Date: Mon, 14 Dec 2020 12:34:01 -0800 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=61015ee87=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- target/riscv/cpu.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))