From patchwork Wed Jun 6 13:31:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 10450299 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1A88960146 for ; Wed, 6 Jun 2018 14:07:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B643293C2 for ; Wed, 6 Jun 2018 14:07:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 001EB2945C; Wed, 6 Jun 2018 14:07:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A913F293C2 for ; Wed, 6 Jun 2018 14:07:08 +0000 (UTC) Received: from localhost ([::1]:52656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQZ5f-0000J8-US for patchwork-qemu-devel@patchwork.kernel.org; Wed, 06 Jun 2018 10:07:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwZ-0008Sc-VR for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000Wp-7h for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44635) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwU-0000W0-0U; Wed, 06 Jun 2018 09:57:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id AEDCB7456B5; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 17C497456BA; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH v2 7/8] sm501: Do not clear read only bits when writing register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP When writing a register that has read only bits besides reserved bits we have to avoid changing read only bits that may have non zero default values. Signed-off-by: BALATON Zoltan --- hw/display/sm501.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index e47be99..7ec1434 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -836,10 +836,10 @@ static void sm501_system_config_write(void *opaque, hwaddr addr, switch (addr) { case SM501_SYSTEM_CONTROL: - s->system_control = value & 0xE300B8F7; + s->system_control |= value & 0xEF00B8F7; break; case SM501_MISC_CONTROL: - s->misc_control = value & 0xFF7FFF20; + s->misc_control |= value & 0xFF7FFF10; break; case SM501_GPIO31_0_CONTROL: s->gpio_31_0_control = value; @@ -853,7 +853,7 @@ static void sm501_system_config_write(void *opaque, hwaddr addr, s->dram_control |= value & 0x7FFFFFC3; break; case SM501_ARBTRTN_CONTROL: - s->arbitration_control = value & 0x37777777; + s->arbitration_control = value & 0x37777777; break; case SM501_IRQ_MASK: s->irq_mask = value;