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Thu, 28 Mar 2019 04:15:24 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1h9T0B-0000L0-B2; Thu, 28 Mar 2019 04:15:19 -0700 Received: from xsj-pvapsmtp01 (mailman.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x2SBF934009883; Thu, 28 Mar 2019 04:15:09 -0700 Received: from [172.23.37.108] (helo=xhdnagasure40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1h9T00-0000Ba-Na; Thu, 28 Mar 2019 04:15:09 -0700 From: Naga Sureshkumar Relli To: , CC: , , , , , , , , , Naga Sureshkumar Relli Subject: [LINUX PATCH 0/3] Add support for Zynq QSPI controller driver Date: Thu, 28 Mar 2019 16:44:52 +0530 Message-ID: <1553771692-30969-1-git-send-email-naga.sureshkumar.relli@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(396003)(376002)(39860400002)(136003)(2980300002)(199004)(189003)(7696005)(316002)(5660300002)(81156014)(426003)(4326008)(81166006)(305945005)(8676002)(2906002)(336012)(7416002)(126002)(36386004)(26005)(2616005)(110136005)(476003)(106002)(486006)(54906003)(51416003)(106466001)(356004)(36756003)(16586007)(14444005)(6666004)(9786002)(63266004)(50466002)(107886003)(478600001)(47776003)(8936002)(50226002)(186003)(48376002)(77096007);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR0201MB3398;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e02b8ae4-24a2-449b-301f-08d6b36ead2d X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4709054)(2017052603328)(7153060);SRVR:DM5PR0201MB3398; X-MS-TrafficTypeDiagnostic: DM5PR0201MB3398: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-Microsoft-Antispam-PRVS: X-Forefront-PRVS: 0990C54589 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: lV5Qi7taTHYCsGDIRk0ccfNbvxnsP6PCn/ioIpBVEsQX4soYszC+M8pLD2uPzhEU5x2ZFSZlA3IqQ3Bwjub37TMveYWczh3sTbd5NBeCB82jy55e9mBde10FceB8ryFtaA91aowSL4IM3iK8bA8Xui8P+4XkOBJpjrK6JoNFlUktqqFmFVvcQTVbYmskR5XINMEx/ZsDUpyhPg4Go7JIl7vTFrhZH06Tg56HlSBY1F3gXNiV2e4NqsI0F1OU4Vd1Nub1QNrc4HzlJK+sEoCKDlP6pE5fLzgGcqjpH99ciO70guaquCCX90Y/KbY8EWRg56teSBwOdwIgbMjALSRzbCNSlaQYKhVkbeTnO8mor/MraeT0U6juf/EIPP9ldPynJjoFrXZhkKEAWPGNGI69oUcy+ur+5YgyKgNL3L+PDbc= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2019 11:15:24.8684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e02b8ae4-24a2-449b-301f-08d6b36ead2d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR0201MB3398 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Xilinx Zynq uses a QSPI controller that implements all the functionality required to support Quad SPI NOR flash devices. This driver along with the SPI MEM and MTD layer is used to support flash devices. The flash device(s) can be connected in three configurations to this controller: 1. Single - One flash device with 1 CS, 1 Clock and 4 IO lines. 2. Dual Parallel - Two flash devices connected with common CS and separate IO lines (resulting in 8 IO lines). In this configuration, the controller a) Duplicates commands, address etc. sent on both sets of 4 IO lines. b) Stripes data both transmitted and received i.e. 4 bits of data is sent to the first flash and the other 4 bits to the second flash. Similarly read data is also consolidated. Due to this, TX and RX data handling in the driver need special handling for parallel mode. 3. Dual Stacked - Two flash devices connected with separate CS and 4 common IO lines. This is largely similar to single, except for the slave selection logic. The above configuration is conveyed to the QSPI driver through a devicetree property(currently not implemented 2 & 3 mentioned above). As per Boris suggestion We are currently not targetting for dual stacked/dual parallel handling. There are changes needed in the framework to handle this. so this update is only for the Single mode. This is tested with spi-v5.0 tag Naga Sureshkumar Relli (3): dt-bindings: spi: Add device tree binding documentation for Zynq QSPI controller spi: spi-mem: call spi_mem_default_supports_op() first spi: spi-mem: Add support for Zynq QSPI controller .../devicetree/bindings/spi/spi-zynq-qspi.txt | 25 + drivers/spi/Kconfig | 10 +- drivers/spi/Makefile | 1 + drivers/spi/spi-mem.c | 7 +- drivers/spi/spi-zynq-qspi.c | 770 +++++++++++++++++++++ 5 files changed, 810 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt create mode 100644 drivers/spi/spi-zynq-qspi.c