From patchwork Mon Apr 15 21:30:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10901625 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E410917E6 for ; Mon, 15 Apr 2019 21:31:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CCDBA286FE for ; Mon, 15 Apr 2019 21:31:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C0F1E28801; Mon, 15 Apr 2019 21:31:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6AF1F286FE for ; Mon, 15 Apr 2019 21:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728162AbfDOVam (ORCPT ); Mon, 15 Apr 2019 17:30:42 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9334 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726751AbfDOVam (ORCPT ); Mon, 15 Apr 2019 17:30:42 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 15 Apr 2019 14:30:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 15 Apr 2019 14:30:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 15 Apr 2019 14:30:41 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 15 Apr 2019 21:30:40 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 15 Apr 2019 21:30:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 15 Apr 2019 21:30:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.253]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 15 Apr 2019 14:30:40 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V3 0/9] bug fixes and more features to Tegra SPI Date: Mon, 15 Apr 2019 14:30:25 -0700 Message-ID: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555363838; bh=irLqmDsEskLEYyTvJn9l0k9bNOUBEg7ana8OjVK+2Kk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=drjx/JKer/gNWcsCgqhY/UPOqHXJ2pdJEeszdxMHDQkr/LxHc9lY5HTbaqxJ8vfLS Od/Z6V8/M3zNKrTaFhsYSOBDF+yVWu+KgRxC4lCYsi3XrKBNbA5+G8FsA0G9/FjzLd 4Cfo3OLJ34pOMoIo0NphvENncYnI3l0OpGU3DD1hvNm279cklm4S5LJhOhgMPlTcv6 1gphnJtxXuGLVcn/A5064uhhs3AIO2fOqL62zfsIVHQ1dXkcFEUL8InvfkfOU34vjG ktxiFbfIZT0m+2bHR2tV/RLhChW9kHuSNzaUlNVrGcGTN2HKvcCmJr6n4GSU9wgv1B Z2tGrUFZ6hfCg== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP [V3] : This patch series version includes - only patches that are not applied from V2. - splitted expanding mode and adding LSByte First support in separate patches and removed DT property for selecting LSByte First. - Updated GPIO based chip select control to use spi_set_cs from SPI core. - HW based chip select implementation is same as V2 but V3 has this patch updated to be on top of above changes. - HW CS timing implementation is same as V2 but V3 has this patch updated to be on top of above changes. - support for TX and RX trimmers implementation is same as V2 but V3 has this patch updated to be on top of above changes and updated commit description. [V2] : This patch series version includes - only patches that are not applied from V1. - changed order of patches to include all fixes prior to new features support. - Removed HW CS timing from DT properties and created set_cs_timing SPI master optional method for SPI controllers to implement and created API spi_cs_timing for SPI client drivers to request CS setup, hold and inactive delay timing configuration. - Fixed HW based CS decision to be based on single transfer and cs_change. Remove selection of HW based CS through DT. Sowjanya Komatineni (9): spi: tegra114: fix PIO transfer spi: expand mode support spi: add SPI_LSBYTE_FIRST mode spi: tegra114: add support for Tegra SPI LSBYTE_FIRST spi: export spi core function spi_set_cs spi: tegra114: add support for gpio based CS spi: tegra114: add support for hw based cs spi: tegra114: add support for HW CS timing spi: tegra114: add support for TX and RX trimmers drivers/spi/spi-tegra114.c | 175 ++++++++++++++++++++++++++++++++++++++++----- drivers/spi/spi.c | 21 +++--- include/linux/spi/spi.h | 8 ++- 3 files changed, 174 insertions(+), 30 deletions(-)