From patchwork Fri Jul 27 12:05:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10546957 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B6CEB112B for ; Fri, 27 Jul 2018 12:05:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A77A02B82D for ; Fri, 27 Jul 2018 12:05:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C12C2B83C; Fri, 27 Jul 2018 12:05:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 328EF2B82D for ; Fri, 27 Jul 2018 12:05:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730709AbeG0N1W (ORCPT ); Fri, 27 Jul 2018 09:27:22 -0400 Received: from mail.bootlin.com ([62.4.15.54]:35160 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729568AbeG0N1W (ORCPT ); Fri, 27 Jul 2018 09:27:22 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id D3A3D2073D; Fri, 27 Jul 2018 14:05:43 +0200 (CEST) Received: from localhost (unknown [88.128.81.178]) by mail.bootlin.com (Postfix) with ESMTPSA id 935A320717; Fri, 27 Jul 2018 14:05:43 +0200 (CEST) From: Alexandre Belloni To: Mark Brown , James Hogan Cc: Paul Burton , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Thomas Petazzoni , Allan Nielsen , Alexandre Belloni Subject: [PATCH v2 0/4] Add support for MSCC Ocelot SPI Date: Fri, 27 Jul 2018 14:05:31 +0200 Message-Id: <20180727120535.16504-1-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.18.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hello, The MSCC MIPS SoC line uses a designware IP for the SPI controller but still requires some special handling to give control of the SPI interface to the IP and also has a specific handling for the chip select. Changes in v2: - Removed already applied patches - separated DT binding changes from the driver patch Alexandre Belloni (4): dt-bindings: spi: snps,dw-apb-ssi: document Microsemi integration spi: dw-mmio: add MSCC Ocelot support mips: dts: mscc: Add spi on Ocelot mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123 arch/mips/boot/dts/mscc/ocelot.dtsi | 11 +++ arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 10 +++ drivers/spi/spi-dw-mmio.c | 91 +++++++++++++++++++++++ 3 files changed, 112 insertions(+)