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bh=+K4qrmUG13QF8xawF1typSHjAy3QdbYQsMd+k3rAD9c=; b=IikPHFbh8Y+cVEJhvxzUjGjKvt6rEaa7JlRxHVUieJptM/pBpRy5fT16dbkyOqg8ltM1dfktLy7DvAJE18JtWDtU6ddlxzzIeaRkLA4NOK4Msx48SnzJ62v1KcC1gM0/ZG3rmPwNlyMUpZ8bcfl8LG2LE8hdYdQab6fYydhJ+vk= Received: from BN6PR11MB1842.namprd11.prod.outlook.com (10.175.98.146) by BN6PR11MB1300.namprd11.prod.outlook.com (10.173.26.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1580.17; Sat, 2 Feb 2019 04:07:11 +0000 Received: from BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f]) by BN6PR11MB1842.namprd11.prod.outlook.com ([fe80::847:4296:13b9:fc9f%8]) with mapi id 15.20.1580.017; Sat, 2 Feb 2019 04:07:10 +0000 From: To: , , , , , , , , CC: , , , , , Subject: [PATCH v3 00/13] spi: atmel-quadspi: introduce sam9x60 qspi controller Thread-Topic: [PATCH v3 00/13] spi: atmel-quadspi: introduce sam9x60 qspi controller Thread-Index: AQHUuqzF5TXyT2EVDU+lmQWhqx0xYg== Date: Sat, 2 Feb 2019 04:07:10 +0000 Message-ID: <20190202040653.1217-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR09CA0062.eurprd09.prod.outlook.com (2603:10a6:802:28::30) To BN6PR11MB1842.namprd11.prod.outlook.com (2603:10b6:404:101::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tudor.Ambarus@microchip.com; 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Patches 12 and 13 introduce the sam9x60 qspi controller. sam9x60 qspi controller tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. The patches are generated on top of for-next branch. v3: - update smm value when different. - treat just regular spi transfers when introducing sam9x60 qspi IP. Mem transfers will be added together with dirmap support. - reorganize the code and change ops functions pointers to avoid code duplication. - rename aq->clk to aq->pclk to indicate that it's a peripheral clock. - drop unused and NOP transfer macros. - add Suggested-by tags, reword some commits. v2: - cache MR value, - drop iomem wrappers, - make "pclk" clock-name mandatory even for sama5d2, - rework clock handling, - reorder setting of register values in set_cfg() calls, - collect R-b tags. Tudor Ambarus (13): spi: atmel-quadspi: cache MR value to avoid a write access spi: atmel-quadspi: order header files inclusion alphabetically spi: atmel-quadspi: drop wrappers for iomem accesses spi: atmel-quadspi: fix naming scheme spi: atmel-quadspi: remove unnecessary cast spi: atmel-quadspi: return appropriate error code spi: atmel-quadspi: switch to SPDX license identifiers spi: atmel-quadspi: drop unused and NOP transfer macros dt-bindings: spi: atmel-quadspi: update example to new clock binding dt-bindings: spi: atmel-quadspi: make "pclk" mandatory spi: atmel-quadspi: add support for named peripheral clock dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 spi: atmel-quadspi: add support for sam9x60 qspi controller .../devicetree/bindings/spi/atmel-quadspi.txt | 12 +- drivers/spi/atmel-quadspi.c | 402 ++++++++++++++------- 2 files changed, 288 insertions(+), 126 deletions(-)