mbox series

[0/7] spi: cadence-quadspi: Add Octal DTR support

Message ID 20201222184425.7028-1-p.yadav@ti.com (mailing list archive)
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Series spi: cadence-quadspi: Add Octal DTR support | expand

Message

Pratyush Yadav Dec. 22, 2020, 6:44 p.m. UTC
Hi,

This series adds support for Octal DTR mode now that SPI NOR supports
these flashes. Patches 1/7 to 4/7 and 6/7 fix some minor bugs and issues.
Patche 5/7 lays some groundwork by implementing the supports_op() hook.
Patch 7/7 adds the Octal DTR mode support.

While the main aim of this series is to support 8D-8D-8D mode, other
modes like 4D-4D-4D or 2S-2S-2S should also now be supported, though
they have not been tested.

Tested on J721E with Micron MT35XU512ABA and on J7200 with Cypress
S28HS512T. Tested on J721E with Micron MT25QU512A (1S-1S-4S) for
regressions.

Pratyush Yadav (7):
  spi: cadence-quadspi: Set master max_speed_hz
  spi: cadence-quadspi: Abort read if dummy cycles required are too many
  spi: cadence-quadspi: Set dummy cycles from STIG commands
  spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
  spi: cadence-quadspi: Implement a simple supports_op hook
  spi: cadence-quadspi: Wait at least 500 ms for direct reads
  spi: cadence-quadspi: Add DTR support

 drivers/spi/spi-cadence-quadspi.c | 364 ++++++++++++++++++++++++++----
 1 file changed, 325 insertions(+), 39 deletions(-)

--
2.28.0

Comments

Mark Brown Jan. 6, 2021, 2:59 p.m. UTC | #1
On Wed, 23 Dec 2020 00:14:18 +0530, Pratyush Yadav wrote:
> This series adds support for Octal DTR mode now that SPI NOR supports
> these flashes. Patches 1/7 to 4/7 and 6/7 fix some minor bugs and issues.
> Patche 5/7 lays some groundwork by implementing the supports_op() hook.
> Patch 7/7 adds the Octal DTR mode support.
> 
> While the main aim of this series is to support 8D-8D-8D mode, other
> modes like 4D-4D-4D or 2S-2S-2S should also now be supported, though
> they have not been tested.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/7] spi: cadence-quadspi: Set master max_speed_hz
      commit: 3a5c09c8d1ed9a7323f0e5c435021531f0865c16
[2/7] spi: cadence-quadspi: Abort read if dummy cycles required are too many
      commit: ceeda328edeeeeac7579e9dbf0610785a3b83d39
[3/7] spi: cadence-quadspi: Set dummy cycles from STIG commands
      commit: 888d517b992532df2b6115fbdc9620673ca7c651
[4/7] spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
      commit: 7512eaf54190e4cc9247f18439c008d44b15022c
[5/7] spi: cadence-quadspi: Implement a simple supports_op hook
      commit: a273596b9b50c76a9cc1f65d3eb7f8ab5c3eb3e3
[6/7] spi: cadence-quadspi: Wait at least 500 ms for direct reads
      commit: 0920a32cf6f20467aa133a47b776ee782daa889f
[7/7] spi: cadence-quadspi: Add DTR support
      commit: f453f293979fb648d2e505c132887811acb6bde6

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark
Pratyush Yadav Jan. 8, 2021, 4:48 p.m. UTC | #2
Hi Mark,

On 06/01/21 02:59PM, Mark Brown wrote:
> On Wed, 23 Dec 2020 00:14:18 +0530, Pratyush Yadav wrote:
> > This series adds support for Octal DTR mode now that SPI NOR supports
> > these flashes. Patches 1/7 to 4/7 and 6/7 fix some minor bugs and issues.
> > Patche 5/7 lays some groundwork by implementing the supports_op() hook.
> > Patch 7/7 adds the Octal DTR mode support.
> > 
> > While the main aim of this series is to support 8D-8D-8D mode, other
> > modes like 4D-4D-4D or 2S-2S-2S should also now be supported, though
> > they have not been tested.
> > 
> > [...]
> 
> Applied to
> 
>    https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
> 
> Thanks!

:-)
 
> [1/7] spi: cadence-quadspi: Set master max_speed_hz
>       commit: 3a5c09c8d1ed9a7323f0e5c435021531f0865c16
> [2/7] spi: cadence-quadspi: Abort read if dummy cycles required are too many
>       commit: ceeda328edeeeeac7579e9dbf0610785a3b83d39
> [3/7] spi: cadence-quadspi: Set dummy cycles from STIG commands
>       commit: 888d517b992532df2b6115fbdc9620673ca7c651
> [4/7] spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1
>       commit: 7512eaf54190e4cc9247f18439c008d44b15022c
> [5/7] spi: cadence-quadspi: Implement a simple supports_op hook
>       commit: a273596b9b50c76a9cc1f65d3eb7f8ab5c3eb3e3
> [6/7] spi: cadence-quadspi: Wait at least 500 ms for direct reads
>       commit: 0920a32cf6f20467aa133a47b776ee782daa889f

The kernel test robot reported some build warnings on this patch on 
32-bit platforms and I was planning on re-rolling it soon. Now that it 
is in your tree, I will send a follow-up patch to fix it.

> [7/7] spi: cadence-quadspi: Add DTR support
>       commit: f453f293979fb648d2e505c132887811acb6bde6
> 
> All being well this means that it will be integrated into the linux-next
> tree (usually sometime in the next 24 hours) and sent to Linus during
> the next merge window (or sooner if it is a bug fix), however if
> problems are discovered then the patch may be dropped or reverted.
> 
> You may get further e-mails resulting from automated or manual testing
> and review of the tree, please engage with people reporting problems and
> send followup patches addressing any issues that are reported if needed.
> 
> If any updates are required or you are submitting further changes they
> should be sent as incremental updates against current git, existing
> patches will not be replaced.
> 
> Please add any relevant lists and maintainers to the CCs when replying
> to this mail.
> 
> Thanks,
> Mark